Ring oscillator using multi-phase signal reassembly
AssigneeNVIDIA Corporation
InventorsChun-Ju Shen, Chien-Heng Wong, Ying Wei
Life of this patent
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Abstract
Technologies for low jitter and low power ring oscillators with multi-phase signal reassembly are described. A ring oscillator circuit includes a ring oscillator with a set of M delay stages, each stage outputs a phase signal, where M is a positive integer greater than one. The ring oscillator circuit includes a phase selector circuit coupled to the ring oscillator. The phase selector circuit can receive M phase signals from the ring oscillator and generate N phase signals based on the M phase signals, where N is a positive integer less than M.
Claims21
A ring oscillator circuit comprising:
- a ring oscillator comprising a set of M delay stages, each stage to output a phase signal, wherein M is a positive integer greater than one;
- and
- a phase selector circuit coupled to the ring oscillator, wherein the phase selector circuit is to:
- receive M phase signals from the ring oscillator;
- and
- generate N phase signals from the M phase signals at a time, wherein N is a positive integer less than M and greater than one, wherein the ring oscillator comprises a first oscillation frequency that is less than a second frequency of the N phase signals.
A Serializer/Deserializer (SERDES) system comprising:
- a transmitter device comprising:
- a serializer;
- a phase-locked loop (PLL) coupled to the serializer, the PLL to provide a first set of N phase signals to the serializer, wherein the PLL comprises:
- a first ring oscillator comprising a first set of M delay stages, each stage to output a phase signal, wherein M is a positive integer greater than one;
- and
- a first phase selector circuit coupled to the first ring oscillator, wherein the first phase selector circuit is to:
- receive a first set of M phase signals from the first ring oscillator;
- and
- generate the first set of N phase signals from the first set of M phase signals at a time, wherein N is a positive integer less than M and greater than one, wherein the first ring oscillator comprises a first oscillation frequency that is less than a second frequency of the N phase signals.
A method of operating a ring oscillator circuit, the method comprising:
- generating M phase signals using M delay stages of a ring oscillator;
- and
- generating N phase signals from the M phase signals at a time, wherein N is a positive integer less than M and greater than one, wherein the ring oscillator comprises a first oscillation frequency that is less than a second frequency of the N phase signals.
An apparatus comprising:
- a ring oscillator to generate M phase signals, wherein M is a positive integer greater than one;
- and
- a phase selector circuit comprising an M-to-N multiplexer coupled to the ring oscillator, wherein the M-to-N multiplexer is to receive the M phase signals from the ring oscillator and select N phase signals from the M phase signals, and wherein N is a positive integer less than M and greater than one, wherein the ring oscillator comprises a first oscillation frequency that is less than a second frequency of the N phase signals.
Dependencies are inferred from the claim text.