Multiplexer and semiconductor device including the same

A multiplexer, comprising:

• a charging circuit including a capacitor charged in response to a first clock signal;
• a plurality of sampling switches configured to receive a plurality of input signals;
• and
• a plurality of boosting circuits connected between the plurality of sampling switches and the charging circuit, and configured to share the charging circuit and operate in response to a second clock signal having a phase opposite to the first clock signal, wherein, when a selected sampling switch and non-selected sampling switches are determined among the sampling switches, a selected boosting circuit among the plurality of boosting circuits, connected to the selected sampling switch, is electrically connected to the charging circuit, and non-selected boosting circuits among the plurality of boosting circuits, connected to the non-selected sampling switches are electrically disconnected from the charging circuit,
• wherein each of the plurality of boosting circuits is connected to or is disconnected from the charging circuit in response to an output signal of a NAND gate receiving the second clock signal and one of a plurality of selection signals.

A semiconductor device, comprising:

• an analog-to-digital converter configured to convert an analog input signal into a digital output signal;
• a multiplexer connected to an input terminal of the analog-to-digital converter and configured to select one of a plurality of analog signals as the analog input signal;
• and
• a plurality of analog circuits configured to output the plurality of analog signals, wherein the multiplexer includes a charging circuit including a capacitor, a plurality of sampling switches, and a plurality of boosting circuits connected between the charging circuit and the plurality of sampling switches,
• wherein each of the plurality of sampling switches is connected between an output terminal of one of the plurality of analog circuits and an input terminal of the analog-to-digital converter, and
• wherein each of the plurality of boosting circuits includes a first boosting switch connected between an upper node of the capacitor and a gate of one of the plurality of sampling switches, a second boosting switch connected between a lower node of the capacitor and a source of the one of the plurality of sampling switches, and a level shifter configured to control the first boosting switch and the second boosting switch,
• wherein a first turn-off voltage input to the first boosting switches connected to the plurality of sampling switches in a pre-charge period in which the plurality of sampling switches are turned off is different from a second turn-off voltage input to the first boosting switches connected to non-selected sampling switches in a boosting period in which the plurality of sampling switches are determined as a selected sampling switch and the non-selected sampling switches and the selected sampling switch is turned on.