Auto calibration dead-time control circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Chun Chang, Alan Roth, Eric Soenen, Tysh-Bin Liu
Life of this patent
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Abstract
Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.
Claims20
A control circuit for controlling dead-time of a direct current to direct current (DC-DC) converter, the control circuit comprising:
- a first transistor comprising a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage;
- a digital up/down counter comprising an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter configured to modify or maintain a delay time of the delay cell to minimize or eliminate the dead-time of the DC-DC converter;
- a current sensing circuit electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current;
- and
- a capacitor electrically coupled between the current sensing circuit and the input terminal of the digital up/down counter.
A method for controlling dead-time of a direct current to direct current (DC-DC) converter, the method comprising:
- providing an output voltage of a DC-DC converter to a first transistor;
- determining, via a current sensing circuit, a control current based on a voltage of the first transistor;
- determining, via a digital up/down counter, a delay count based on the control current;
- providing the delay count to a delay cell;
- and
- providing current to a second transistor electrically coupled to the current sensing circuit, wherein a gate terminal of the second transistor is electrically coupled to a reference voltage.
A direct current to direct current (DC-DC) circuit comprising:
- one or more delay cells;
- a control circuit comprising a current sensing circuit, a first transistor, and a digital up/down counter;
- the control circuit further comprising an output electrically coupled to an input of the one or more delay cells;
- and
- a high side circuit and a low side circuit coupled to the one or more delay cells and configured to provide an output voltage;
- wherein:
- the first transistor is configured to be operational based on the output voltage and a gate voltage of the first transistor;
- the current sensing circuit is configured to either modify or maintain a count of the digital up/down counter;
- and
- the digital up/down counter is configured to modify or maintain a delay time of the one or more delay cells to minimize or eliminate the dead-time of the DC-DC circuit.
Dependencies are inferred from the claim text.