US 11,961,917 B2Granted

Semiconductor device comprising stacked transistors

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsKazuya Hanaoka, Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shunpei Yamazaki, Shinpei Matsuda

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Abstract

Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.

Claims8

Dependent claims

A semiconductor device comprising:

a first transistor;
and
a second transistor over the first transistor,
wherein a channel of the first transistor comprises silicon,
wherein a first semiconductor layer in which a channel of the second transistor is formed comprises indium, gallium, and zinc,
wherein part of a bottom surface of a first conductive layer functioning as one of a source and a drain of the second transistor is positioned below the first semiconductor layer,
wherein part of a bottom surface of a second conductive layer functioning as the other of the source and the drain of the second transistor is positioned below the first semiconductor layer,
wherein the first conductive layer and the second conductive layer are in contact with a top surface of the first semiconductor layer,
wherein a first insulating layer is provided over the first semiconductor layer,
wherein a third conductive layer functioning as a gate of the second transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the third conductive layer,
wherein a third insulating layer is provided over the second insulating layer, the first conductive layer and the second conductive layer,
wherein a fourth conductive layer is provided over and in contact with the third insulating layer,
wherein a fifth conductive layer functioning as a gate of the first transistor is provided over the channel of the first transistor with a fourth insulating layer provided therebetween,
wherein the first transistor is electrically connected to the second transistor,
wherein a fifth insulating layer is provided over and overlapping with the fifth conductive layer,
wherein the first semiconductor layer is in contact with a top surface of the fifth insulating layer, and
wherein the first conductive layer is not in contact with a bottom surface of the first semiconductor layer.

15 more elements

A semiconductor device comprising:

a first transistor;
and
a second transistor over the first transistor,
wherein a channel of the first transistor comprises silicon,
wherein a first semiconductor layer of the second transistor in which a channel is formed comprises an oxide semiconductor,
wherein part of a bottom surface of a first conductive layer functioning as one of a source and a drain of the second transistor is positioned below the first semiconductor layer,
wherein part of a bottom surface of a second conductive layer functioning as the other of the source and the drain of the second transistor is positioned below the first semiconductor layer,
wherein the first conductive layer and the second conductive layer are in contact with a top surface of the first semiconductor layer,
wherein a first insulating layer is provided over the first semiconductor layer,
wherein a third conductive layer functioning as a gate of the second transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the third conductive layer,
wherein a third insulating layer is provided over the second insulating layer, the first conductive layer and the second conductive layer,
wherein a fourth conductive layer is provided over and in contact with the third insulating layer,
wherein a fifth conductive layer functioning as a gate of the first transistor is provided over the channel of the first transistor with a fourth insulating layer provided therebetween,
wherein the first transistor is electrically connected to the second transistor,
wherein a fifth insulating layer is provided over and overlapping with the fifth conductive layer,
wherein the first semiconductor layer is in contact with a top surface of the fifth insulating layer, and
wherein the first conductive layer is not in contact with a bottom surface of the first semiconductor layer.

15 more elements

A semiconductor device comprising:

a first transistor;
and
a second transistor over the first transistor,
wherein a channel of the first transistor comprises silicon,
wherein a first semiconductor layer in which a channel of the second transistor is formed comprises indium, gallium, and zinc,
wherein part of a bottom surface of a first conductive layer functioning as one of a source and a drain of the second transistor is positioned below the first semiconductor layer,
wherein part of a bottom surface of a second conductive layer functioning as the other of the source and the drain of the second transistor is positioned below the first semiconductor layer,
wherein the first conductive layer and the second conductive layer are in contact with a top surface of the first semiconductor layer,
wherein a first insulating layer is provided over the first semiconductor layer,
wherein a third conductive layer functioning as a gate of the second transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the third conductive layer,
wherein a third insulating layer is provided over the second insulating layer, the first conductive layer and the second conductive layer,
wherein a fourth conductive layer functioning as a gate of the first transistor is provided over the channel of the first transistor,
wherein a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer are provided over the channel of the first transistor,
wherein the second conductive layer is electrically connected to the channel of the first transistor via a first opening in the fourth insulating layer, a second opening in the fifth insulating layer, and a third opening in the sixth insulating layer,
wherein a bottom surface of the third conductive layer is provided below the top surface of the first semiconductor layer,
wherein the first semiconductor layer is in contact with a top surface of the sixth insulating layer,
wherein the sixth insulating layer overlaps with the fourth conductive layer, and
wherein the first conductive layer is not in contact with a bottom surface of the first semiconductor layer.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/844,767Filed 21 Jun 2022 · continuation
Priority: JP 2013-10628420 May 2013
Published: US 2022/0328694 A113 Oct 2022
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 30/6729
Thin-film transistors [TFT]: characterised by the electrodes
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]

Family

Application14/277,465Parent of this continuation · filed 14 May 2014
Application15/617,696Parent of this continuation · filed 8 Jun 2017
US 9,722,088 B2Parent of this continuation · filed 1 Aug 2017
Application16/710,456Parent of this continuation · filed 11 Dec 2019
US 10,573,758 B2Parent of this continuation · filed 25 Feb 2020
US 2022/0328694 A1Pre-grant publication · published 13 Oct 2022
US 11,430,894 B2Parent of this continuation
US 2014/0339544 A1Published application
US 2017/0271523 A1Published application
US 2020/0119201 A1Published application
US 11,961,917 B2This patent

From the US filing history. Foreign family members aren’t listed.