US 11,961,916 B2Granted

Memory device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsTatsuya Onuki, Kiyoshi Kato, Tomoaki Atsumi, Shunpei Yamazaki

Life of this patent

Estimating the term…

Loading patent…

Abstract

A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

Claims15

Dependent claims

A memory device comprising:

a plurality of first wirings extending in a first direction;
a plurality of oxide layers;
and
a first memory element group and a second memory element group,
wherein the plurality of first wirings comprise a region overlapping with the first memory element group, and a region overlapping with the second memory element group,
wherein one of the plurality of oxide layers comprises a region extending along a side surface of one of the first wirings,
wherein the first memory element group and the second memory element group comprise a plurality of memory elements,
wherein each of the plurality of memory elements comprises a transistor and a capacitor,
wherein in each of the plurality of memory elements, a gate electrode of the transistor is electrically connected to one of the plurality of first wirings, and a semiconductor layer of the transistor comprises a region in contact with one of the plurality of oxide layers, and
wherein a shortest distance from the gate electrode of the transistor included in the memory cell positioned in an end portion of the first memory element group to the gate electrode of the transistor included in the memory cell positioned in an end portion of the second memory element group is less than or equal to 3.5 μm.

7 more elements

A memory device comprising:

a plurality of first wirings extending in a first direction;
a plurality of oxide layers;
and
a first memory element group;
a second memory element group;
and a first region,
wherein the plurality of first wirings comprise a region overlapping with the first memory element group, a region overlapping with the second memory element group, and a region overlapping with the first region,
wherein one of the plurality of oxide layers comprises a region extending along a side surface of one of the first wirings,
wherein the first memory element group and the second memory element group comprise a plurality of memory elements,
wherein each of the plurality of memory elements comprises a first transistor and a capacitor,
wherein in each of the plurality of memory elements, a gate of the first transistor is electrically connected to one of the plurality of first wirings, and a semiconductor layer of the first transistor comprises a region in contact with one of the plurality of oxide layers,
wherein the first region comprises a plurality of second transistors,
wherein in each of the plurality of second transistors, a gate electrode is electrically connected to one of the plurality of first wirings, and one or both of a source electrode and a drain electrode are electrically connected to a fourth wiring, and
wherein a function of supplying a high power supply potential to the fourth wiring is provided.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/261,665Filed 29 Jul 2019
Priority: JP 2018-1503879 Aug 2018
Published: US 2021/0273110 A12 Sep 2021
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits