US 11,961,909 B2Granted

Semiconductor device including a MISFET and method of manufacturing the same

AssigneeRenesas Electronics Corporation

InventorHideki Sugiyama

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Abstract

Semiconductor device includes a well region formed in an active region of a semiconductor substrate, a gate electrode formed on the well region via a gate dielectric film, and a source region and a drain region formed in the well region. At the vicinity of both end portions of the active region in the first direction, a first region and a second region having the same conductivity type as the well region and having impurity concentration higher than that of the well region are formed in the well region. The first region and the second region are spaced from each other in a second direction perpendicular to the first direction, and at least a portion of each of them is located under the gate electrode. The first region and the second region are not formed at the center portion of the active region in the first direction.

Claims16

Dependent claims

A semiconductor device including a MISFET, the semiconductor device comprising:

a semiconductor substrate having a main surface, an element isolation region embedded in a trench of the main surface, and an active region surrounded by the element isolation region;
a well region of a first conductivity type, the well region being formed in the active region of the semiconductor substrate;
a gate electrode of the MISFET, the gate electrode being formed on the well region of the semiconductor substrate via a gate dielectric film and extending in a first direction;
and
a source region of the MISFET and a drain region of the MISFET, each of the source region and the drain region being formed in the well region, having a second conductivity type opposite the first conductivity type and spaced from each other in a second direction perpendicular to the first direction,
wherein the source region includes:
a first semiconductor region;
and
a first high concentration region adjacent to the first semiconductor region and having an impurity concentration higher than that of the first semiconductor region,
wherein the drain region includes:
a second semiconductor region;
and
a second high concentration region adjacent to the second semiconductor region and having an impurity concentration higher than that of the second semiconductor region,
wherein the first semiconductor region and the second semiconductor region are spaced from each other in the second direction via a region directly below the gate electrode,
wherein a first region of the first conductivity type is formed in the well region and is in contact with the first semiconductor region and the element isolation region,
wherein a second region of the first conductivity type is formed in the well region and is in contact with the first semiconductor region and the element isolation region,
wherein the first region and the second region are spaced apart from each other in the first direction,
wherein a third region of the first conductivity type is formed in the well region and is in contact with the second semiconductor region and the element isolation region,
wherein a fourth region of the first conductivity type is formed in the well region and is in contact with the second semiconductor region and the element isolation region,
wherein the third region and the fourth region are spaced apart from each other in the first direction,
wherein the first region and the third region are spaced apart from each other in the second direction, and each has an impurity concentration higher than that of the well region,
wherein the second region and the fourth region are spaced from each other in the second direction, and each has an impurity concentration higher than that of the well region, and
wherein at least a portion of the first region and at least a portion of the second region are located under the gate electrode.

20 more elements

A method of manufacturing a semiconductor device including a MISFET, comprising the steps of:

(a) preparing a semiconductor substrate having a main surface, an element isolation region embedded in a trench of the main surface, and an active region surrounded by the element isolation region;
(b) forming a well region of a first conductivity type in the active region of the semiconductor substrate;
(c) after the (b), forming a gate electrode of the MISFET on the well region of the semiconductor substrate via a gate dielectric film, the gate electrode extending in a first direction;
(d) after the (c), by a first ion implantation, forming a first semiconductor region and a second semiconductor region each having a second conductivity type opposite the first conductivity type in the well region, the first semiconductor region and the second semiconductor region being spaced from each other via a region directly below the gate electrode in a second direction perpendicular to the first direction;
(e) after the (c), by a second ion implantation, forming a first region of the first conductivity type and a second region of the first conductivity type spaced from each other in the second direction in the well region, each of the first region and the second region having an impurity concentration higher than that of the well region;
(f) after the (d) and after the (e), forming a sidewall spacer on each of both sidewalls of the gate electrode;
and
(g) after the (f), by a third ion implantation, forming a first high concentration region of the second conductivity type in the well region, the first high concentration region having an impurity concentration higher than that of the first semiconductor region, and forming a second high concentration region of the second conductivity type in the well region, the second high concentration region having an impurity concentration higher than that of the second semiconductor region,
wherein a source region of the MISFET is formed by the first semiconductor region and the first high concentration region,
wherein a drain region of the MISFET is formed by the second semiconductor region and the second high concentration region,
wherein the first region is adjacent to the first semiconductor region, the second region is adjacent to the second semiconductor region, and at least a portion of the first region and at least a portion of the second region are located under the gate electrode, and
wherein the first region and the second region are formed at a vicinity of both end portions of the active region in the first direction, while the first region and the second region are not formed at a center portion of the active region in the first direction.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/686,042Filed 3 Mar 2022
Published: US 2023/0282745 A17 Sep 2023
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/605
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having significant overlap between the lightly-doped extensions…
H10D 30/0218
Of FETs having insulated gates [IGFET]: having pocket halo regions selectively formed at the sides of the gates
H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates