Vertical transistor and method for fabricating the same

#The present application claims priority of Korean Patent Application No. 10-2021-0003864, filed on Jan. 12, 2021, which is herein incorporated by reference in its entirety.

#The present invention disclosure relates to a vertical transistor and a method of manufacturing the same, and, more specifically, to a vertical transistor using an oxide semiconductor as a channel layer and a method of manufacturing the same.

#As memory devices are highly integrated, technologies for applying vertical transistors have been proposed to increase the density of transistors. Technologies for applying an oxide semiconductor having excellent electrical characteristics as a channel material for vertical transistors have also been proposed.

#FIG. 1 is a perspective view illustrating a vertical transistor according to an embodiment;

#FIG. 2 is a perspective view illustrating an upper contact, lower contact, and channel layer of a vertical transistor according to an embodiment;

#FIGS. 3A, 3C, 3D, 3E, 3F, 3G, 3H, and 3I are views illustrating an example method for manufacturing a vertical transistor according to an embodiment;

#Example cross-sectional views, plan views, and block diagrams may be used herein to describe various embodiments of the disclosure, and modifications may be made thereto according to, e.g., manufacturing techniques and/or tolerances. Thus, embodiments of the disclosure are not limited to specific types as shown and illustrated herein but may rather encompass changes or modifications resultant from fabricating processes. For example, the regions or areas shown in the drawings may be schematically shown, and their shapes shown are provided merely as examples, rather as limiting the category or scope of the disclosure. Elements shown in the drawings may be exaggerated in light of their thicknesses and intervals for illustration purposes. Well known components or elements irrelevant to the subject matter of the disclosure may be omitted from the description. The same or substantially the same reference denotations are used to refer to the same or substantially the same elements throughout the specification and the drawings. Hereinafter, embodiments of the disclosure are described in detail with reference to the accompanying drawings.

#FIG. 1 is a perspective view illustrating a vertical transistor according to an embodiment.

#As illustrated in FIG. 1, a vertical transistor 100 may include a stack structure including a lower contact 110, a channel layer 120, and an upper contact 130. The vertical transistor 100 may further include a dielectric layer 140 and gate 150 formed on a side surface of the channel layer 120. That is, the lower contact 110, the channel layer 120, and the upper contact 130 may have a stack structure in a direction extending perpendicular to a substrate (not shown), while the dielectric layer 140 and the gate 150 may have a stack structure in a direction extending parallel to the substrate (not shown).