Power semiconductor device and method of fabricating the same

A power semiconductor device comprising:

• a semiconductor layer of silicon carbide (SiC);
• a plurality of trenches extending in parallel in one direction and recessed into the semiconductor layer from a surface of the semiconductor layer;
• a gate insulating layer disposed on at least inner walls of the trenches;
• a gate electrode layer disposed on the gate insulating layer and including a plurality of portions respectively disposed in the plurality of trenches;
• a drift region including a plurality of vertical portions disposed in the semiconductor layer between the plurality of portions of the gate electrode layer, and having a first conductivity type;
• a well region disposed in the semiconductor layer to be deeper than the plurality of portions of the gate electrode layer, so as to be in contact with the plurality of vertical portions of the drift region and to surround bottom surfaces of the plurality of portions of the gate electrode layer at opposite ends of the plurality of portions of the gate electrode layer, and having a second conductivity type;
• a source region disposed in the well region and having the first conductivity type;
• and
• a plurality of channel regions disposed in the semiconductor layer of opposite sides of the plurality of portions of the gate electrode layer between the plurality of vertical portions of the drift region and the source region, and having the second conductivity type,
• wherein the gate electrode layer continuously extends from one of the plurality of trenches to another of the plurality of trenches so as to continuously cover an upper surface of the source region between the one of the plurality of trenches and the another of the plurality of trenches.

A method of fabricating a power semiconductor device, comprising:

• forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC);
• forming a well region being in contact with at least a part of the drift region and having a second conductivity type, in the semiconductor layer;
• forming a source region having the first conductivity type, in the well region;
• forming at least one channel region having the second conductivity type, in the semiconductor layer between the drift region and the source region;
• forming at least one trench to be shallower than the well region, so as to be recessed into the semiconductor layer from a surface of the semiconductor layer to extend across the drift region in one direction;
• forming a gate insulating layer on at least an inner wall of the at least one trench;
• and
• forming at least one gate electrode layer on the gate insulating layer and in the at least one trench,
• wherein the well region is formed in the semiconductor layer to be deeper than the at least one gate electrode layer, so as to surround a bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer, and
• wherein the channel region is formed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region,
• wherein the forming of the source region includes:
• forming a source contact region connected with a source electrode layer outside the one end of the at least one gate electrode layer,
• wherein the method further comprises:
• forming, in the source contact region, a well contact region extending through the source region from the well region, connected with the source electrode layer, and having the second conductivity type,
• wherein a doping concentration of the well contact region is higher than a doping concentration of the well region.