Semiconductor device with multichannel heterostructure and manufacturing method thereof

A semiconductor device, comprising:

• a semiconductor heterostructure layer, comprising alternating first semiconductor material layers and second semiconductor material layers, wherein a two-dimensional electron gas (2DEG) can be generated between each first semiconductor material layer and its adjacent second semiconductor material layer;
• a drain structure, comprising a plurality of first conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer, wherein the plurality of first conductive fingers are arranged in a first direction substantially parallel to the surface, and wherein lengths of the plurality of first conductive fingers progressively increase in the first direction so that an end portion of each first conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG;
• a source structure, comprising a plurality of second conductive fingers extending from the surface into the semiconductor heterostructure layer, wherein the plurality of second conductive fingers are arranged in the first direction, and wherein lengths of the plurality of second conductive fingers progressively decrease in the first direction so that an end portion of each second conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG;
• and
• a gate structure, disposed between the drain structure and the source structure.

A method for manufacturing a semiconductor device, comprising:

• forming a semiconductor heterostructure layer, comprising alternatively forming first semiconductor material layers and second semiconductor material layers, wherein a two-dimensional electron gas (2DEG) can be generated between each first semiconductor material layer and its adjacent second semiconductor material layer;
• and
• patterning a surface of the semiconductor heterostructure layer to form a plurality of openings in a first direction substantially parallel to the surface of the semiconductor heterostructure layer;
• and
• etching the semiconductor heterostructure layer from the plurality of openings so as to form a plurality of trenches in the semiconductor heterostructure layer, wherein depths of the plurality of trenches progressively increase in the first direction, the etching stops in different second semiconductor material layers, and a bottom of each trench is not in contact with the 2DEG;
• depositing a conductive material in the plurality of trenches so as to form a conductive structure;
• and
• performing annealing at an annealing temperature;
• wherein cross areas of the plurality of openings progressively increase in the first direction.