Semiconductor device having nanosheet transistor and methods of fabrication thereof

A semiconductor device structure, comprising;

• a plurality of semiconductor layers vertically stacked;
• a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers;
• a high-k (HK) dielectric layer in contact with the gate electrode layer;
• a source/drain feature in contact with each semiconductor layer of the plurality of semiconductor layers;
• and
• a dielectric spacer disposed between the HK dielectric layer and the source/drain feature, wherein the dielectric spacer has a first side in contact with the source/drain feature and a second side in contact with the HK dielectric layer, and the second side comprising:
• a first section has a first curved surface having a first radius of curvature;
• and
• a second section has a second curved surface having a second radius of curvature different than the first radius of curvature,
• wherein the first section and the second section are connected and formed as an integral.

A method for forming a semiconductor device structure, comprising:

• forming first and second fin structures each comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;
• forming a sacrificial layer on exposed sidewall surfaces of the first and second fin structures;
• forming a sacrificial gate structure over a portion of the first and second fin structures and the sacrificial layer;
• removing portions of the first and second fin structures and the sacrificial layer not covered by the sacrificial gate structure;
• removing edge portions of the sacrificial layer and edge portions of each of the plurality of second semiconductor layers in the first and second fin structures to form cavities, wherein edge portions of the sacrificial layer are etched at a first amount and edge portions of each of the plurality of second semiconductor layers are etched at a second amount less than the first amount;
• forming a dielectric spacer in the cavities;
• forming an epitaxial source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the dielectric spacer and each of the plurality of first semiconductor layers in the first and second fin structures;
• removing the sacrificial layer and the second semiconductor layers to expose portions of each of the plurality of first semiconductor layers of the first and second fin structures;
• and
• forming a gate electrode layer to surround each of the plurality of first semiconductor layers of the first and second fin structures.