US 11,961,885 B2Granted

Semiconductor device

AssigneeSony Semiconductor Solutions Corporation

InventorsTetsuo Gocho, Yuzo Fukuzaki, Shinichi Miyake, Kazuyuki Tomida

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Abstract

A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2≥(L1/2) is satisfied.

Claims15

Dependent claims

A semiconductor device, comprising:

a base;
a first field effect transistor, wherein the first field effect transistor is disposed on a first side of the base, and wherein the first field effect transistor includes:
a first channel portion;
a second channel portion, wherein the first channel portion is disposed between the second channel portion and the base;
and
a first insulation layer, wherein the first insulation layer is disposed between the first channel portion and the base;
a second field effect transistor, wherein the second field effect transistor is disposed on the first side of the base, and wherein the second field effect transistor includes:
a channel forming layer;
a gate insulation layer, wherein at least a portion of the gate insulation layer is between the channel forming layer and the base;
a gate electrode, wherein at least a portion of the gate electrode is between the gate insulation layer and the base;
and
a second insulation layer,
wherein the second insulation layer is between the gate electrode and the base, and
wherein a thickness of the second insulation layer is larger than a thickness of the first insulation layer.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/943,337Filed 13 Sep 2022 · continuation
Priority: JP 2018-14021726 Jul 2018
Published: US 2023/0006042 A15 Jan 2023
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

H10D 62/121
Nanowire, nanosheet or nanotube semiconductor bodies: oriented parallel to substrates
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 30/0193
Forming stacked channels, e.g. changing their shapes or sizes: by modifying properties of the stacked channels
H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…

Family

PCT/JP2019/024075Parent of this continuation · filed 18 Jun 2019
US 2023/0006042 A1Pre-grant publication · published 5 Jan 2023
Application17/261,226Parent of this continuation
US 11,476,329 B2Parent of this continuation
US 2021/0280673 A1Published application
US 11,961,885 B2This patent

From the US filing history. Foreign family members aren’t listed.