US 11,961,880 B2Granted

Metal-insulator-metal structure

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsYuan-Yang Hsiao, Hsiang-Ku Shen, Tsung-Chieh Hsiao, Ying-Yao Lai, Dian-Hau Chen

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Abstract

A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.

Claims20

Dependent claims

A semiconductor device, comprising:

a first metal-insulator-metal structure comprising:
a first bottom conductor plate,
a first portion of a first dielectric layer over the first bottom conductor plate,
a first middle conductor plate over the first portion of the first dielectric layer,
a first portion of a second dielectric layer over the first middle conductor plate, and
a first top conductor plate over the first portion of the second dielectric layer;
and
a second metal-insulator-metal structure comprising:
a second bottom conductor plate,
a second portion of the first dielectric layer over the second bottom conductor plate,
a second middle conductor plate over the second portion of the first dielectric layer,
a second portion of the second dielectric layer over the second middle conductor plate, and
a second top conductor plate over the second portion of the second dielectric layer,
wherein in a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the second top conductor plate.

11 more elements

A semiconductor structure, comprising:

a substrate;
a first metal layer over the substrate;
a first insulating layer over the first metal layer;
a second metal layer over the first insulating layer;
a second insulating layer over the second metal layer;
a third metal layer over the second insulating layer, and
first, second, and third plugs through the metal layer, the first insulating layer, the second metal layer, the second insulating layer, and the third metal layer,
wherein a first metal-insulator-metal structure includes a first portion of the first metal layer, a first portion of the second metal layer, and a first portion of the third metal layer that are stacked vertically one over another, wherein a second metal-insulator-metal structure includes a second portion of the first metal layer, a second portion of the second metal layer, and a second portion of the third metal layer that are stacked vertically one over another,
wherein the first plug is insulated from the first portion of the first metal layer, the first portion of the second metal layer, and the first portion of the third metal layer, wherein the second plug is insulated from the first portion of the first metal layer and the first portion of the third metal layer and is electrically connected to the first portion of the second metal layer, wherein the third plug is electrically connected to the first portion of the first metal layer and the first portion of the third metal layer and is insulated from the first portion of the second metal layer,
wherein the first and the second portions of the first metal layer are adjacent to each other and there is no other portion of the first metal layer in between,
wherein the first and the second portions of the second metal layer are adjacent to each other and there is no other portion of the second metal layer in between,
wherein the first and the second portions of the third metal layer are adjacent to each other and there is no other portion of the third metal layer in between,
wherein along a first direction, the first portion of the first metal layer is wider than the second portion of the first metal layer, and the first portion of the third metal layer is narrower than the second portion of the third metal layer.

10 more elements

A semiconductor structure, comprising:

a substrate;
a first metal layer over the substrate;
a first insulating layer over the first metal layer;
a second metal layer over the first insulating layer;
a second insulating layer over the second metal layer;
and
a third metal layer over the second insulating layer,
wherein a first metal-insulator-metal structure includes a first portion of the first metal layer, a first portion of the second metal layer, and a first portion of the third metal layer that are stacked vertically one over another, wherein a second metal-insulator-metal structure includes a second portion of the first metal layer, a second portion of the second metal layer, and a second portion of the third metal layer that are stacked vertically one over another,
wherein in a cross-sectional view, the first portion of the first metal layer is wider than the second portion of the first metal layer, the first portion of the third metal layer is narrower than the second portion of the third metal layer, the first portion of the first metal layer is wider than the first portion of the second metal layer, and the second portion of the first metal layer is narrower than the second portion of the second metal layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/397,400Filed 9 Aug 2021 · us provisional application
Priority: 6 May 2021
Published: US 2022/0359644 A110 Nov 2022
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 1/043
Of capacitors having no potential barriers: using patterning processes to form electrode extensions, e.g. etching
H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
H10D 1/68
Capacitors: capacitors having no potential barriers
H10D 1/714
Having non-planar surfaces, e.g. formed by texturisation: having horizontal extensions