Interconnect layout for semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Hsiung Tsai, Shahaji B. More, Yu-Ming Lin, Clement Hsingjen Wann
Life of this patent
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Abstract
A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.
Claims20
A semiconductor device comprising:
- a substrate;
- a deep trench capacitor (DTC) having a portion within a deep trench in the substrate;
- and
- an interconnect structure over the DTC and the substrate, the interconnect structure comprising:
- a seal ring structure in electrical contact with the substrate, the seal ring structure surrounding a circuitry;
- a first conductive line in electrical contact with the DTC;
- and
- a second conductive line over the first conductive line, wherein the first conductive line electrically couples the second conductive line to the DTC, wherein a portion of one of the first conductive line or a second conductive line is a part of the seal ring structure, wherein the one of the first conductive line or the second conductive line is part of the circuitry.
A semiconductor device comprising:
- a substrate, the substrate having a doped region;
- a deep trench capacitor (DTC) partially within the substrate;
- an interconnect structure over the DTC and the substrate, the interconnect structure comprising:
- a seal ring structure in electrical contact with the substrate, the doped region being in physical contact with the seal ring structure;
- a first conductive via in physical contact with the DTC, the first conductive via being in electrical contact with the seal ring structure;
- and
- a first conductive line over the first conductive via, the first conductive via electrically coupling the first conductive line to the DTC, the seal ring structure electrically coupling the first conductive line to the substrate;
- and
- a contact pad over the interconnect structure, the contact pad being electrically coupled to the substrate through the seal ring structure, wherein the contact pad is in physical contact with the first conductive line.
A semiconductor device comprising:
- a substrate;
- a doped region in the substrate;
- a deep trench capacitor (DTC) having a portion in a trench in the substrate adjacent the doped region, wherein the doped region is spaced apart from the trench;
- an interconnect structure over the DTC and the substrate, the interconnect structure comprising:
- a first conductive via in physical contact with the doped region;
- a first conductive line over the first conductive via, the first conductive line being in electrical contact with the DTC;
- a second conductive line over the first conductive line, the second conductive line being in electrical contact with the first conductive via and the first conductive line;
- and
- a contact pad over the interconnect structure, the contact pad being electrically coupled to the doped region through the second conductive line and the first conductive via, wherein the second conductive line is in physical contact with the contact pad.
Dependencies are inferred from the claim text.