US 11,961,877 B1Granted

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures

AssigneeKepler Computing Inc.

InventorsSomilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Pratyush Pandey, Jason Y. Wu, Sasikanth Manipatruni

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Abstract

A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Claims16

Dependent claims

A device comprising:

a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
and
a second level above the first level, the second level comprising:
an electrode structure on the first conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer;
and
a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness;
an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure;
a second dielectric on the etch stop layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material;
a trench within the second dielectric, the trench on the electrode structure;
a memory device within the trench, the memory device comprising:
a first electrode along a base and a sidewall of the trench, wherein the first electrode is in contact with the electrode structure;
a dielectric layer comprising a ferroelectric material or a paraelectric material substantially conformal to the first electrode;
and
a second electrode in contact with the dielectric layer;
and
a via electrode on the second electrode, the via electrode comprising:
a second conductive hydrogen barrier layer comprising a lateral portion in contact with the second electrode and substantially vertical portions connected to the lateral portion;
and
a second conductive fill material adjacent to the second conductive hydrogen barrier layer;
and
a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the first level;
and
a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material;
and
a via structure on the second conductive interconnect, the via structure laterally in contact with the third dielectric.

25 more elements

A system comprising:

a processor;
a communication interface communicatively coupled to the processor;
and
a memory coupled to the processor, wherein the memory comprises:
bit-cells, wherein one of the bit-cells includes:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
a second level above the first level, the second level comprising:
an electrode structure on the first conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer;
and
a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness;
an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure;
a second dielectric on the etch stop layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material;
a trench within the second dielectric, the trench on the electrode structure;
a memory device within the trench, the memory device comprising:
a first electrode along a base and a sidewall of the trench, wherein the first electrode is in contact with the electrode structure;
a dielectric layer comprising a ferroelectric material or a paraelectric material substantially conformal to the first electrode;
and
a second electrode in contact with the dielectric layer;
and
a via electrode on the second electrode, the via electrode comprising:
a second conductive hydrogen barrier layer comprising a lateral portion in contact with the second electrode and substantially vertical portions connected to the lateral portion;
and
a second conductive fill material adjacent to the second conductive hydrogen barrier layer;
and
a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the first level;
and
a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material;
and
a via structure on the second conductive interconnect, the via structure laterally in contact with the third dielectric.

29 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/550,899Filed 14 Dec 2021
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
H10B 51/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region
H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
H10D 1/043
Of capacitors having no potential barriers: using patterning processes to form electrode extensions, e.g. etching