Semiconductor device having nanosheet transistor and methods of fabrication thereof

A semiconductor device structure, comprising:

• a first gate electrode layer;
• a second gate electrode layer disposed below and in contact with the first gate electrode, the second gate electrode layer comprising a material chemically different than the first gate electrode layer;
• a first intermixed layer in contact with a portion of the first gate electrode layer, the first intermixed layer comprising a first material having a first polarity;
• a second intermixed layer in contact with a portion of the second gate electrode layer and the first intermixed layer, the second intermixed layer comprising a second material having a second polarity opposite of the first polarity;
• a high-K (HK) dielectric layer in contact with a portion of the first intermixed layer;
• and
• a third intermixed layer in contact with a portion of the second intermixed layer and the HK dielectric layer, the third intermixed layer comprising a third material having the first polarity.

A method for forming a semiconductor device structure, comprising:

• forming a plurality of first semiconductor layers vertically stacked;
• forming a first source/drain feature and a second source/drain feature disposed at a level higher than the first source/drain feature, wherein the first source/drain feature and the second source/drain feature are in contact with the plurality of first semiconductor layers;
• forming a first dipole layer to surround a first group of the plurality of first semiconductor layers, wherein the first dipole layer comprises a first dipole material having a first polarity;
• forming a second dipole layer to surround a second group of the plurality of first semiconductor layers, wherein the second dipole layer comprises a second dipole material having a second polarity opposite of the first polarity;
• and
• subjecting the first and second dipole layers to a first thermal treatment.