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US 11,961,832 B2Granted
Integrated circuit device
AssigneeSamsung Electronics Co., Ltd.
InventorsJina Lee, Hyungjoo Youn
Life of this patent
Estimating the term…
Abstract
An integrated circuit device includes a substrate having a first intellectual property (IP) core including a cell region and a first edge dummy region, fin-type active regions protruding from the cell region, dummy fin-type active regions protruding from the first edge dummy region, gate lines extending, over the cell region of the substrate, the gate lines including two adjacent gate lines spaced apart from each other with a first pitch and two adjacent gate lines spaced apart with a second pitch greater than the first pitch, dummy gate lines over the first edge dummy region of the substrate and equally spaced apart from each other with the first pitch.
Claims20
An integrated circuit device comprising:
- a substrate having an intellectual property (IP) core, which is surrounded by a separation region and has at least two first edges extending in a first horizontal direction and at least two second edges extending in a second horizontal direction that intersects the first horizontal direction, the IP core comprising a cell region and an edge dummy region that is arranged to extend along the at least two second edges;
- a plurality of fin-type active regions in the cell region, extending in the first horizontal direction;
- a plurality of dummy fin-type active regions in the edge dummy region;
- a plurality of nanosheet stack structures spaced apart from top surfaces of the plurality of fin-type active regions and the plurality of dummy fin-type active regions, and each of the plurality of nanosheet stack structures comprising a plurality of nanosheets, and disposed on each of the top surfaces of the plurality of fin-type active regions and the plurality of dummy fin-type active regions, a plurality of gate lines in the cell region, extending in the second horizontal direction, which intersects the first horizontal direction;
- and
- a plurality of dummy gate lines in the edge dummy region,
- wherein the edge dummy region is disposed between the separation region and the cell region, and
- wherein a length, in the second horizontal direction, of the edge dummy region is the same as a length, in the second horizontal direction, of the cell region.
5 more elements
An integrated circuit device comprising:
- a substrate having a plurality of intellectual property (IP) core, each of the plurality of IP core surrounded by a separation region, having at least two first edges extending in a first horizontal direction and at least two second edges extending in a second horizontal direction that intersects the first horizontal direction, and comprising a cell region and an edge dummy region that is arranged to extend along the at least two second edges;
- a plurality of dummy fin-type active regions in the edge dummy region;
- a plurality of fin-type active regions in the cell region, extending in the first horizontal direction;
- a plurality of nanosheet stack structures disposed on top surfaces of the plurality of fin-type active regions and spaced apart from the top surfaces of the plurality of fin-type active regions, each of the plurality of nanosheet stack structures comprising a plurality of nanosheets;
- a first device isolation film, which defines the plurality of fin-type active regions and the plurality of dummy fin-type active regions, and fills a lower portion of a first trench disposed between two fin-type active regions, adjacent to each other, of the plurality of fin-type active regions, and between two dummy fin-type active regions, adjacent to each other, of the plurality of dummy fin-type active regions, the first trench having a bottom surface at a first vertical level;
- a second device isolation film filling a second trench, the second trench extending through the first device isolation film and having a bottom surface at a second vertical level that is lower than the first vertical level;
- a plurality of gate lines in the cell region, extending in the second horizontal direction, which intersects the first horizontal direction;
- and
- a plurality of dummy gate lines in the edge dummy region, wherein the edge dummy region is disposed between the separation region and the cell region,
- wherein a length, in the second horizontal direction, of the edge dummy region is the same as a length, in the second horizontal direction, of the cell region, and
- wherein a portion of the second device isolation film between two adjacent IP cores among the plurality of IP core is formed in one body.
8 more elements
An integrated circuit device comprising:
- a substrate having a plurality of intellectual property (IP) core, each of the plurality of IP core surrounded by a separation region, having at least two first edges extending in a first horizontal direction and at least two second edges extending in a second horizontal direction that intersects the first horizontal direction, and comprising a cell region and an edge dummy region that is arranged to extend along the at least two second edges;
- a plurality of dummy fin-type active regions in the edge dummy region, and spaced apart from each other by a first pitch in the edge dummy region;
- a plurality of fin-type active regions in the cell region, extending in the first horizontal direction;
- a plurality of nanosheet stack structures disposed on top surfaces of the plurality of fin-type active regions and spaced apart from the top surfaces of the plurality of fin-type active regions, each of the plurality of nanosheet stack structures comprising a plurality of nanosheets;
- a plurality of gate lines in the cell region, extending in the second horizontal direction, which intersects the first horizontal direction;
- a plurality of dummy gate lines in the edge dummy region, and spaced apart from each other by a second pitch in the edge dummy region;
- a first device isolation film, which defines the plurality of fin-type active regions and fills a lower portion of a first trench disposed between two fin-type active regions, adjacent to each other, of the plurality of fin-type active regions, the first trench having a bottom surface at a first vertical level;
- and
- a second device isolation film filling a second trench, the second trench extending through the first device isolation film and having a bottom surface at a second vertical level that is lower than the first vertical level,
- wherein the edge dummy region is disposed between the separation region and the cell region, and
- wherein a length, in the second horizontal direction, of the edge dummy region is the same as a length, in the second horizontal direction, of the cell region,
- wherein the second device isolation film, in the separation region, is configured to enclose the each of the plurality of IP core and extend along each of at least two first edges and each of at least two second edges,
- wherein a portion of the second device isolation film between respective first edges of two adjacent IP cores among the plurality of IP cores is formed in one body, and
- wherein two portions of the second device isolation film, which extend to surround mutually-facing respective second edges of two adjacent IP cores among the plurality of IP core is spaced apart from each other.
11 more elements
Dependencies are inferred from the claim text.