3D semiconductor device and structure with metal layers

A semiconductor device, the device comprising:

• a first substrate;
• a first metal layer disposed over said first substrate;
• a second metal layer disposed over said first metal layer;
• a first level comprising a single crystal layer and a plurality of transistors, said first level disposed over said second metal layer,
• wherein an average thickness of said single crystal layer is less than one micron;
• a third metal layer disposed over said first level;
• a fourth metal layer disposed over said third metal layer,
• wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error;
• and
• a via disposed through said first level, and
• wherein processing of said single crystal layer to said thickness comprises use of at least one etch rate selectivity.

A semiconductor device, the device comprising:

• a first substrate;
• a first metal layer disposed over said first substrate;
• a second metal layer disposed over said first metal layer;
• a first level comprising a plurality of transistors, said first level disposed over said second metal layer,
• wherein said plurality of transistors comprise single crystal silicon;
• a third metal layer disposed over said first level;
• a fourth metal layer disposed over said third metal layer,
• wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error;
• a global power distribution network;
• a local power distribution network,
• wherein said global power distribution network comprises said fourth metal layer, and
• wherein said local power distribution network comprises said third metal layer;
• and
• at least one direct contact,
• wherein said at least one direct contact connects at least one of said plurality of transistors to said third metal layer.