Semiconductor package including stacked chip structure
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunggyun Noh, Sangwoo Pae, Jinsoo Bae, Iljoo Choi, Deokseon Choi, Keunho Rhew
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AssigneeSamsung Electronics Co., Ltd.
InventorsHyunggyun Noh, Sangwoo Pae, Jinsoo Bae, Iljoo Choi, Deokseon Choi, Keunho Rhew
Estimating the term…
A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.
A semiconductor package comprising:
A semiconductor package comprising:
A semiconductor package comprising:
Dependencies are inferred from the claim text.