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US 11,961,812 B2Granted
Semiconductor packages having vias
AssigneeSamsung Electronics Co., Ltd.
InventorsChangeun Joo, Gyujin Choi
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.
Claims20
A semiconductor package comprising:
- a lower redistribution layer including an insulating pattern having an opening and a via in the opening;
- a first semiconductor chip on the lower redistribution layer, the first semiconductor chip including a chip pad on a lower surface of the first semiconductor chip, a passivation layer, and a pad bump, the pad bump extending through the passivation layer and being connected to the chip pad;
- and
- a first encapsulant on the lower redistribution layer and the first semiconductor chip,
- wherein the opening of the insulating pattern defines a lower surface and an outer side surface of the pad bump, and
- wherein the via includes a central protrusion in physical contact with the lower surface of the pad bump;
- a first portion in physical contact with a lower surface of the passivation layer and the outer side surface of the pad bump;
- and a second portion spaced apart from the passivation layer.
5 more elements
A semiconductor package comprising:
- a lower redistribution layer including an insulating pattern having a first opening and a second opening, a first via in the first opening, and a second via in the second opening;
- a first semiconductor chip on the lower redistribution layer, the first semiconductor chip including a chip pad, a passivation layer, and a pad bump, the pad bump extending through the passivation layer and being connected to the chip pad;
- a first encapsulant on the lower redistribution layer and the first semiconductor chip, and
- a connection member on the lower redistribution layer adjacent to the first semiconductor chip, the connection member including an insulating layer and a conductive pad between the insulating layer and the lower redistribution layer,
- wherein the second opening defines a lower surface and a side surface of the conductive pad, and
- the second via is in physical contact with the insulating layer and the lower surface of the conductive pad and at least a portion of the side surface of the conductive pad.
3 more elements
A semiconductor package comprising:
- a lower package comprising:
- a lower redistribution layer including an insulating pattern having an opening and a via in the opening;
- a first semiconductor chip on the lower redistribution layer, the first semiconductor chip including a chip pad, a passivation layer, and a pad bump, the pad bump extending through the passivation layer and being connected to the chip pad;
- a connection member on the lower redistribution layer adjacent to the first semiconductor chip;
- a first encapsulant on the lower redistribution layer and the first semiconductor chip;
- and
- an upper redistribution layer on an upper surface of the first encapsulant and electrically connected to the connection member,
- wherein the via physically contacts a portion of the outer side surface of the pad bump,
- wherein the insulating pattern physically contacts a remaining portion of the outer side surface of the pad bump, and
- wherein the via includes a central protrusion in physical contact with the lower surface of the pad bump;
- a first portion in physical contact with a lower surface of the passivation layer and the outer side surface of the pad bump;
- and a second portion spaced apart from the passivation layer.
9 more elements
Dependencies are inferred from the claim text.