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US 11,961,795 B2Granted
Semiconductor package and package-on-package including the same
AssigneeSamsung Electronics Co., Ltd.
InventorBongken Yu
Life of this patent
Estimating the term…
Abstract
A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.
Claims20
A method of manufacturing a semiconductor package, the method comprising:
- attaching a semiconductor chip and a plurality of lower conductive solders onto a support wiring structure;
- forming a preliminary filling member surrounding the semiconductor chip and the plurality of lower conductive solders on the support wiring structure, the preliminary filling member including a plurality of fillers;
- forming a lower filling unit and a plurality of lower connection units by removing an upper portion of the preliminary filling member and upper portions of the plurality of lower conductive solders until upper surfaces of the lower filling unit and the plurality of lower connection units are positioned at a reference level;
- attaching a plurality of upper conductive solders under a cover wiring structure;
- arranging the cover wiring structure on the support wiring structure so that the plurality of lower connection units and the plurality of upper conductive solders correspond to each other;
- forming a plurality of connection structures that are one body by soldering the plurality of lower connection units and the plurality of upper conductive solders corresponding to each other by performing a reflow process, each of the plurality of connection structures including the lower connection unit and an upper connection unit;
- and
- forming a filling member including the lower filling unit and an upper filling unit, the upper filling unit is formed by filling a gap between the lower filling unit and the cover wiring structure;
- wherein a partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along the reference level.
6 more elements
A method of manufacturing a semiconductor package, the method comprising:
- attaching a semiconductor chip and a plurality of lower conductive solders onto a support wiring structure;
- forming a preliminary filling member surrounding the semiconductor chip and the plurality of lower conductive solders on the support wiring structure and including a plurality of fillers;
- forming a lower filling unit and a plurality of lower connection units by removing an upper portion of the preliminary filling member and upper portions of the plurality of lower conductive solders;
- attaching a plurality of upper conductive solders under a cover wiring structure;
- arranging the cover wiring structure on the support wiring structure so that the plurality of lower connection units and the plurality of upper conductive solders correspond to each other;
- forming a plurality of connection structures that are one body by soldering the plurality of lower connection units and the plurality of upper conductive solders corresponding to each other by performing a reflow process, each of the plurality of connection structures including the lower connection unit and an upper connection unit;
- and
- forming an upper filling unit by filling a gap between the lower filling unit and the cover wiring structure.
5 more elements
A method of manufacturing a semiconductor package, the method comprising:
- attaching a plurality of semiconductor chips and a plurality of lower conductive solders onto a support wiring structure array;
- forming a preliminary filling member surrounding the plurality of semiconductor chips and the plurality of lower conductive solders on the support wiring structure array and including a plurality of fillers;
- forming a lower filling unit and a plurality of lower connection units by removing an upper portion of the preliminary filling member, upper portions of the plurality of lower conductive solders, and upper portions of the plurality of semiconductor chips;
- attaching a plurality of upper conductive solders under a cover wiring structure array;
- arranging the cover wiring structure array on the support wiring structure array so that the plurality of lower connection units and the plurality of upper conductive solders correspond to each other;
- forming a plurality of connection structures that are one body by soldering the plurality of lower connection units and the plurality of upper conductive solders corresponding to each other by performing a reflow process, each of the plurality of connection structures including the lower connection unit and an upper connection unit;
- forming a filling member including the lower filling unit and an upper filling unit, the upper filling unit is formed by filling a gap between the lower filling unit and the cover wiring structure array;
- and
- individualizing the support wiring structure array and the cover wiring structure array into support wiring structures and cover wiring structures corresponding to each other,
- wherein a partial portion of the plurality of fillers includes cutting fillers, and
- wherein each of upper surfaces of the cutting fillers is a flat surface as seen in a cross-sectional view.
8 more elements
Dependencies are inferred from the claim text.