Structure and process of integrated circuit having latch-up suppression
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
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Abstract
A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
Claims20
A method of forming an integrated circuit, the method comprising:
- forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate;
- form a first fin active region extruded from the N-well and a second fin active region extruded from the P-well;
- forming a first isolation feature inserted between and vertically extending through the N-well and the P-well;
- and
- forming a second isolation feature overlying the N-well and the P-well and laterally disposed between the first and the second fin active regions.
A semiconductor structure, comprising:
- a semiconductor substrate;
- a deep trench isolation feature extending into the semiconductor substrate;
- a n-type doped well (N-well) disposed in the semiconductor substrate and along a first sidewall of the deep trench isolation feature;
- and
- a p-type doped well (P-well) disposed in the semiconductor substrate adjacent to the N-well and along a second sidewall of the deep trench isolation feature, wherein a bottom surface of the deep trench isolation feature is below bottom surfaces of the N-well and the P-well.
A method of forming an integrated circuit, the method comprising:
- receiving a design layout of the integrated circuit having an inverter that includes a n-type field effect transistor and a p-type field effect transistor sharing a gate;
- modifying the design layout such that the gate of the inverter has an end aligned to a common edge of a n-type doped well (N-well) and a p-type doped well (P-well);
- and
- fabricating the integrated circuit according to the modified design layout, wherein fabricating of the integrated circuit includes:
- forming the N-well and P-well in a semiconductor substrate;
- forming a deep trench isolation feature extending through the common edge of the N-well and P-well;
- forming the gate over the N-well and the P-well;
- and
- forming a gate-cut feature extends through the gate such that the gate-cut feature is vertically aligned with the common edge of the N-well and P-well.
Dependencies are inferred from the claim text.