Semiconductor device and method of making a wafer-level chip-scale package

A semiconductor device, comprising:

• a semiconductor die including a contact pad;
• an encapsulant deposited over the semiconductor die;
• and
• a fan-in interconnect structure formed over the semiconductor die, wherein the fan-in interconnect structure includes,
• a first insulating layer formed over the semiconductor die including a first opening formed through the first insulating layer to expose the contact pad,
• a second insulating layer formed over the first insulating layer including a second opening formed through the second insulating layer to expose the contact pad,
• a conductive layer formed over the first insulating layer and second insulating layer, wherein the conductive layer extends through the first opening and second opening to contact the contact pad, and
• a third insulating layer formed over and directly on the conductive layer and second insulating layer, wherein side surfaces of the semiconductor die, first insulating layer, second insulating layer, and third insulating layer are all coplanar to each other.

A semiconductor device, comprising:

• a semiconductor die;
• an encapsulant deposited over the semiconductor die, wherein a side surface of the semiconductor die is exposed from the encapsulant;
• and
• a fan-in interconnect structure formed over the semiconductor die, wherein the fan-in interconnect structure includes,
• a first insulating layer formed over the semiconductor die,
• a second insulating layer formed over the first insulating layer,
• a conductive layer formed over the first insulating layer and second insulating layer, and
• a third insulating layer formed over the conductive layer;
• wherein a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, a side surface of the semiconductor die, and a side surface of the encapsulant are all coplanar to each other.