Variable page size architecture
AssigneeMicron Technology, Inc.
InventorCorrado Villa
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.
Claims20
A method, comprising:
- receiving an access request for a memory cell in a memory bank of a memory array that includes a plurality of memory sections, each memory section having a plurality of physical rows of memory cells;
- identifying a memory section of the plurality of memory sections of the memory bank in which the memory cell is located;
- identifying, in the memory section, a physical row of the plurality of physical rows of memory cells that comprises the memory cell;
- identifying, in the physical row, a memory page that comprises the memory cell, wherein the physical row comprises a first quantity of memory cells selectively coupled with a second quantity of sense components, wherein each sense component is selectively coupled with a respective plurality of memory cells of the physical row, and the memory page comprises a third quantity of memory cells equal to the second quantity of sense components, the first quantity greater than the second quantity;
- and
- generating a logic row address to open the memory page.
A memory system, comprising:
- processing circuitry associated with one or more memory devices, wherein the processing circuitry is configured to cause the memory system to:
- receive an access request for a memory cell in a memory bank of a memory array that includes a plurality of memory sections, each memory section having a plurality of physical rows of memory cells;
- identify a memory section of the plurality of memory sections of the memory bank in which the memory cell is located;
- identify, in the memory section, a physical row of the plurality of physical rows of memory cells that comprises the memory cell;
- identify, in the physical row, a memory page that comprises the memory cell, wherein the physical row comprises a first quantity of memory cells selectively coupled with a second quantity of sense components, wherein each sense component is selectively coupled with a respective plurality of memory cells of the physical row, and the memory page comprises a third quantity of memory cells equal to the second quantity of sense components, the first quantity greater than the second quantity;
- and
- generate a logic row address to open the memory page.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by processing circuitry to:
- receive an access request for a memory cell in a memory bank of a memory array that includes a plurality of memory sections, each memory section having a plurality of physical rows of memory cells;
- identify a memory section of the plurality of memory sections of the memory bank in which the memory cell is located;
- identify, in the memory section, a physical row of the plurality of physical rows of memory cells that comprises the memory cell;
- identify, in the physical row, a memory page that comprises the memory cell, wherein the physical row comprises a first quantity of memory cells selectively coupled with a second quantity of sense components, wherein each sense component is selectively coupled with a respective plurality of memory cells of the physical row, and the memory page comprises a third quantity of memory cells equal to the second quantity of sense components, the first quantity greater than the second quantity;
- and
- generate a logic row address to open the memory page.
Dependencies are inferred from the claim text.