Clock driver and memory device comprising the same

A memory device, comprising:

• a plurality groups of memory chips;
• and
• a clock driver, comprising:
• an input multiplexer for receiving a plurality pairs of input clock signals and an input selection signal, and for selectively outputting one pair of the plurality pairs of input clock signals according to the input selection signal;
• a phase locking loop (PLL) coupled to the input multiplexer to receive one pair of the plurality pairs of input clock signals, and for generating a PLL clock signal according to the received pair of input clock signals;
• at least two sets of output multiplexers coupled to the PLL to receive the PLL clock signal and an output selection signal, wherein each set of output multiplexers are configured to selectively output the PLL clock signal as a set of output clock signals according to the output selection signal to drive at least one group of memory chips;
• and
• a control module configured to detect toggling of the plurality pairs of input clock signals and generate the input selection signal and the output selection signal based on a detection result of the toggling of the plurality pairs of input clock signals.

A method for clocking a memory device, wherein the method comprises:

• detecting, via a control module, toggling of a plurality pairs of input clock signals and generating an input selection signal and an output selection signal based on a detection result of the toggling of the plurality pairs of input clock signals;
• selectively outputting, via an input multiplexer, one pair of the plurality pairs of input clock signals according to the input selection signal;
• generating, via a phase locking loop (PLL), a PLL clock signal based on the pair of input clock signals received from the input multiplexer;
• and
• outputting, via at least two sets of output multiplexers, the PLL clock signal as a set of output clock signals to at least one group of memory chips to drive the at least one group of memory chips.