Semiconductor device, memory system, and method of correcting duty cycle of output signal from semiconductor device
AssigneeKioxia Corporation
InventorKensuke Yamamoto
Life of this patent
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Abstract
A semiconductor device according to an embodiment includes: a logic control circuit to which a signal is input; a timing information storage circuit configured to store timing information related to a start timing of correction processing that corrects a duty cycle of the signal; and a sequencer configured to start execution of the correction processing based on the timing information when a command related to the execution of the correction processing is received.
Claims12
A semiconductor device comprising:
- an input circuit to which a signal is input;
- a timing information storage circuit configured to store timing information related to a start timing of correction processing that corrects a duty cycle of the signal;
- and
- a control circuit configured to start the correction processing in response to a command instructing execution of the correction processing to correct the duty cycle of the signal, at a timing corresponding to the timing information stored in the timing information storage circuit,
- wherein the timing information is a set value of a frequency that the signal received toggles.
A memory system comprising:
- a first semiconductor storage device;
- a second semiconductor storage device;
- and
- a controller configured to control data writing to and data reading from the first semiconductor storage device and second semiconductor storage device, wherein
- the first semiconductor storage device includes
- a first input circuit to which a signal from the controller is input,
- a first timing information storage circuit configured to store first timing information related to a start timing of first correction processing that corrects a duty cycle of the signal in the first semiconductor storage device, and
- a first control circuit configured to start the first correction processing in response to a command instructing execution of the first correction processing, the first correction processing being started at a first timing corresponding to the first timing information, and
- the second semiconductor storage device includes
- a second input circuit to which a signal from the controller is input,
- a second timing information storage circuit configured to store second timing information related to a start timing of second correction processing that corrects a duty cycle of the signal in the second semiconductor storage device, and
- a second control circuit configured to start the second correction processing in response to the command, the second correction processing being started at a second timing corresponding to the second timing information.
A method of correcting a duty cycle of an output signal from a semiconductor device, the method comprising:
- inputting a signal;
- receiving a command instructing execution of correction processing that corrects a duty cycle of the input signal;
- and
- starting the correction processing in response to the command at a timing corresponding to timing information related to a start timing of the correction processing, the time information being stored in a timing information storage circuit,
- wherein the timing information is a set value of a frequency that the signal received toggles.
Dependencies are inferred from the claim text.