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US 11,961,585 B2Granted
Centralized placement of command and address swapping in memory devices
OwnerKazuhiro Yoshidainventor
Life of this patent
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Abstract
Memory devices are disclosed. A memory device may include a bonding pad region for coupling command-and-address (CA) input signals and a memory cell region for storing information in memory cells. The memory device may also include a centralized CA interface region including input circuits coupled to the CA input signals. At least two of the input circuits are configured in pairs. Each pair includes a swap circuit configured to select one of a first CA output and a second CA output for a first internal CA signal and select the other of the first CA output and the second CA output for a second internal CA signal responsive to a control signal. Memory systems and systems are also disclosed.
Claims20
A memory device, comprising:
- a. centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals;
- and
- a clock buffer circuit adjacent to at least one of the two or more CA input circuits and configured to supply one or more clock signals to each of the two or more CA input circuits;
- wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
- a first CA input circuit and a second CA input circuit adjacently arranged in a mirror relationship;
- a first swap circuit configured to:
- select, for a first operation, a first CA output for a first internal CA signal;
- and
- select, for a second, different operation, the first CA output for a second internal CA signal;
- and
- a second swap circuit configured to:
- select, for the first operation, a second CA output for the second internal CA signal;
- and
- select, for the second, different operation, the second CA output for the first internal CA signal.
11 more elements
A memory device comprising:
- a centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals;
- wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
- a first CA input circuit and a second CA input circuit adjacently arranged in a mirror relationship;
- and
- a swap circuit configured to:
- select for a first operation, one of a first CA output and a second CA output for a first internal CA signal and the other of the first CA output and the second CA output for a second internal CA signal responsive to a control signal being in a first state;
- and
- select, for a second, different operation, the one of the first CA output and the second CA output for the second internal CA signal and the other of the first CA output and the second CA output for the first internal CA signal responsive to the control signal being in a second, different state;
- wherein the centralized CA interface region:
- is configured in a layout arrangement such that the two or more CA input circuits comprises eight CA input circuits adjacently arranged in a two-by-four matrix;
- and
- includes a clock buffer circuit adjacent to at least one of the two or more CA input circuits.
9 more elements
A memory system, comprising:
- a number of memory devices, each memory device of the number comprising:
- a centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals, wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
- a first CA input circuit including a first swap circuit for selecting a first CA output as a first internal CA signal when a control signal is negated;
- and
- a second CA input circuit including a second swap circuit for selecting a second CA output as a second internal CA signal when the control signal is negated, the CA input circuit and the second CA input circuit arranged in a mirror relationship with the first swap circuit positioned adjacent the second swap circuit.
2 more elements
A system, comprising:
- one or more processors;
- a memory controller operably coupled to the one or more processors;
- and
- one or more memory devices operably coupled to the memory controller, each memory device of the one or more memory devices comprising:
- a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more CA input signals;
- a memory cell region for storing information in a number of memory cells;
- and
- a centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals;
- wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
- a first CA input circuit and a second CA input circuit positioned adjacent the first CA input circuit in a mirror relationship;
- wherein the first CA input circuit includes a first swap circuit configured to:
- select, for a first operation;a first CA output for a first internal CA signal;
- select for a second, different operation, the first CA output for a second internal CA signal, and
- wherein the second CA input circuit includes a second swap circuit adjacent the first swap circuit and configured to:
- select, for the first operation, second CA output for the second internal CA signal;
- and
- select for the second, different operation, the second CA output for the first internal CA signal.
14 more elements
Dependencies are inferred from the claim text.