Semiconductor storage device and method of controlling the same
AssigneeKioxia Corporation
InventorsAkio Sugahara, Yoshikazu Harada, Shoichiro Hashimoto
Life of this patent
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Abstract
In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.
Claims18
A NAND memory device comprising:
- a bus;
- and
- a group of NAND dies, each of the group of NAND dies coupled to the bus, the group of NAND dies including:
- a first NAND die configured to:
- transmit through the bus, at a first time, a first set of bits related to a first peak current, the first peak current associated with a first operation on the first NAND die, and
- a second NAND die configured to:
- transmit through the bus, at a second time after the first time, a second set of bits related to a second peak current, the second peak current associated with a second operation on the second NAND die, and
- pause, at a third time after the second time, executing the second operation on the second NAND die, based on an indication that the second peak current cannot be provided,
- wherein the indication is based on the transmission of the first set of bits and the second set of bits.
Dependencies are inferred from the claim text.