Single “A” latch with an array of “B” latches

An integrated circuit (IC) comprising:

• an input clock;
• a first scan latch, coupled to the input clock, and having a first output and enabled to load data during a first part of a period of the input clock;
• a clocking circuit, coupled to the input clock, having a first address input, and outputting a plurality of latch clocks with a latch clock of the plurality of latch clocks driven to an active state during a second part of the period of the input clock dependent on the first address input;
• a first set of two or more storage elements having inputs coupled to the first output of the first scan latch, storage elements of the first set of two or more storage elements respectively coupled to a latch clock of the plurality of latch clocks, a storage element of the first set of two or more storage elements enabled to load data during a time that its respective latch clock is in an active state;
• a selector circuit having inputs respectively coupled to outputs of the first set of two or more storage elements and having a second address input and a selector output, the selector circuit configured to output a first value from one output of the outputs of the first set of two or more storage elements on the selector output based on the second address input;
• a second scan latch coupled to the selector output enabled to load data during the first part of the input clock period;
• and
• a scan chain that includes the first scan latch and the second scan latch.