Semiconductor device and reading method
AssigneeWinbond Electronics Corp.
InventorsMakoto Senoo, Sho Okabe
Life of this patent
Estimating the term…
Abstract
The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).
Claims15
A reading method of a NAND flash memory, which comprises a bit line selection circuit selecting an even-numbered bit line or an odd-numbered bit line and a page buffer/reading circuit connected to the bit line selection circuit, the reading method comprising:
- a first step of precharging a selected bit line with a supply voltage of a first voltage supply source connected to the bit line selection circuit;
- and
- a second step of initializing a latch of the page buffer/reading circuit with a supply voltage of a second voltage supply source connected to the page buffer/reading circuit in parallel with precharging of the selected bit line.
A semiconductor device, comprising:
- a NAND memory cell array;
- a reading component reading data from a selected page of the memory cell array;
- and
- an output component outputting the data read by the reading component to outside,
- wherein the reading component comprises a bit line selection circuit selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit,
- the reading component precharges a selected bit line with a supply voltage of a first voltage supply source connected to the bit line selection circuit, and initializes a latch of the page buffer/reading circuit with a supply voltage of a second voltage supply source connected to the page buffer/reading circuit in parallel with precharging of the selected bit line.
Dependencies are inferred from the claim text.