US 11,961,567 B2Granted

Key storage device and key generation method

AssigneePUFsecurity Corporation

InventorsKai-Hsin Chuang, Chi-Yi Shao, Chun-Heng You

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Abstract

A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

Claims20

Dependent claims

A key storage device, comprising:

a first key unit, configured to output a first logic value through a first node, comprising:
a first setting circuit configured to output a first setting voltage;
and
a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value;
and
a second key unit, configured to output a second logic value through a second node, comprising:
a second setting circuit configured to output a second setting voltage;
and
a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value,
wherein an absolute value of the first threshold voltage is lower than an absolute value of the second threshold voltage,
wherein the first setting voltage is higher than the second setting voltage, and
wherein the first setting circuit and the second setting circuit comprises a first setting transistor and a second setting transistor, respectively, receiving a constant voltage at a control terminal.

9 more elements

A key generation method, comprising:

generating a first setting voltage by a first setting circuit;
transmitting the first setting voltage to a first output transistor in a first inverter to generate a first logic value, wherein the first output transistor has a first threshold voltage;
generating a second setting voltage by a second setting circuit;
and
transmitting the second setting voltage to a second output transistor in a second inverter to generate a second logic value, wherein the second output transistor has a second threshold voltage,
wherein an absolute value of the first threshold voltage is lower than an absolute value of the second threshold voltage,
wherein the first setting voltage is higher than the second setting voltage, and
wherein the first setting circuit and the second setting circuit comprises a first setting transistor and a second setting transistor, respectively, receiving a constant voltage at a control terminal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/848,409Filed 24 Jun 2022 · us provisional application
Priority: 21 Sep 2021
Published: US 2023/0091881 A123 Mar 2023
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 21/72
To assure secure computing or processing of information: in cryptographic circuits
G11C 16/22
Auxiliary circuits, e.g. for writing into memory: safety or protection circuits preventing unauthorised or accidental access to memory cells
G06F 21/79
To assure secure storage of data: in semiconductor storage media, e.g. directly-addressable memories
G11C 7/24
Arrangements for writing information into, or reading information out from, a digital store: memory cell safety or protection circuits, e.g.…