Fast bit erase for upper tail tightening of threshold voltage distributions

A method comprising:

• causing a plurality of wordlines of a memory device to be discharged after a program pulse programs one or more memory cells coupled with a selected wordline of the plurality of wordlines;
• initially causing unselected wordlines of the plurality of wordlines to be charged to a first voltage level to boost a channel voltage in memory cells coupled with a second pillar, wherein a first pillar is coupled with a first data line, the second pillar is coupled with a second data line, and the plurality of wordlines are coupled with the first pillar and the second pillar;
• after a period of time, causing the unselected wordlines to be charged to a second voltage level that is higher than the first voltage level;
• causing a supply voltage to be applied to the second data line to cause a voltage of the second pillar to float;
• initially causing a ground voltage to be applied to the first data line to inhibit soft erase via the first pillar;
• during the period of time, transitioning to cause the supply voltage to be applied to the first data line to also cause a voltage of the first pillar to float;
• and
• causing one of the ground voltage or a negative voltage to be applied to the selected wordline to increase a soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be partially erased.

A method comprising:

• causing a plurality of wordlines to be discharged after a program pulse programs one or more memory cells coupled with a selected wordline of the plurality of wordlines;
• causing a ground voltage to be applied to a first data line to inhibit soft erase via a first pillar that is coupled with the first data line and the plurality of wordlines;
• causing a supply voltage to be applied to a second data line to cause a voltage of a second pillar to float, the second pillar coupled with the plurality of wordlines and the first data line;
• causing unselected wordlines, of the plurality of wordlines, to be charged to boost channel voltages in memory cells coupled with the second pillar;
• and
• causing one of the ground voltage or a negative voltage to be applied to the selected wordline to increase a soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be partially erased.