Multi-program of memory cells without intervening erase operations
AssigneeMicron Technology, Inc.
InventorEzra Edward Hartz
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic is to perform operations including: causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level; and causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second erase distribution programmed relative to the first Vt level and a second voltage distribution programmed relative to a second Vt level.
Claims18
A memory device comprising:
- an array of memory cells configured as single-level cell memory;
- and
- control logic operatively coupled with the array of memory cells, the control logic to perform operations comprising:
- causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level;
- and
- causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising a second erase distribution programmed relative to a second Vt level and a second voltage distribution programmed relative to a third Vt level, wherein the second Vt level is higher than the first Vt level and the third Vt level is higher than the second Vt level.
A method comprising:
- causing, by control logic of a memory device comprising an array of memory cells configured as single-level cell memory, first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising a first erase distribution programmed below an erase Vt level and a first voltage distribution programmed relative to a first Vt level;
- and
- causing, by the control logic, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising a second erase distribution programmed relative to a second Vt level and a second voltage distribution programmed relative to a third Vt level, wherein the second Vt level is higher than the first Vt level and the third Vt level is higher than the second Vt level.
A method comprising:
- causing, by control logic of a memory device comprising an array of memory cells configured as multi-level cell memory, first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising an erase distribution programmed below an erase Vt level and multiple first voltage distributions programmed relative to multiple first Vt levels;
- and
- causing, by the control logic without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising multiple second voltage distributions programmed relative to multiple second Vt levels, the multiple second Vt levels being higher than a highest Vt level of the multiple first Vt levels.
Dependencies are inferred from the claim text.