Nonvolatile memory device with intermediate switching transistors and programming method

A method of programming in a nonvolatile memory device, the nonvolatile memory device comprising a cell region including a plurality of first metal pads and a peripheral region including a plurality of second metal pads and vertically connected to the cell region by the plurality of first metal pads and the plurality of second metal pads, the method comprising:

• providing a memory block in the cell region, the memory block comprising a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings connected to a plurality of bit lines, each cell string comprising a plurality of memory cells connected in series and disposed in the vertical direction;
• providing a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent sub blocks in the vertical direction;
• and
• selectively activating, by a control circuit in the peripheral region, each of the plurality of intermediate switching transistors based on a program address during a program operation,
• wherein selectively activating each of the plurality of intermediate switching transistors includes turning on one or more intermediate switching transistors in a selected cell string and turning off one or more intermediate switching transistors in an unselected cell string adjacent to the selected cell string in a first direction, based on the program address, and
• wherein the selected cell string and the unselected cell string are connected to a first bit line of the plurality of bit lines.

A method of programming in a nonvolatile memory device, the nonvolatile memory device comprising a cell region including a plurality of first metal pads and a peripheral region including a plurality of second metal pads and vertically connected to the cell region by the plurality of first metal pads and the plurality of second metal pads, the method comprising:

• providing a memory block in the cell region, the memory block comprising a first sub block below a stopper layer and a second sub block above the stopper layer where the memory block includes a plurality of cell strings connected to a plurality of bit lines, each cell string comprising a plurality of memory cells connected in series and disposed in a vertical direction;
• providing a plurality of intermediate switching transistors disposed in the stopper layer;
• turning on, by a control circuit in the peripheral region, one or more intermediate switching transistors in a selected cell string in response to a first string selection transistor connected to a first bit line of the plurality of bit lines in the selected cell string being activated during a program operation;
• and
• turning off, by the control circuit, the one or more intermediate switching transistors in an unselected cell string adjacent to the selected cell string in a first direction in response to a second string selection transistor connected to the first bit line in the unselected cell string being inactivated during the program operation.