US 11,961,563 B2 · Balancing peak power with programming speed in non-volatile memory

Abstract

Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying within the allowed peak Icc.

Claims20

Dependent claims

An apparatus comprising:

one or more control circuits configured to connect to a three-dimensional memory structure comprising a plurality of NAND strings having memory cells, each memory cell having a control gate, the three-dimensional memory structure comprising a plurality of word lines, each word line being connected to the control gates of memory cells on a group of the NAND strings, wherein the one or more control circuits are configured to:
program memory cells in a selected block in the three-dimensional memory structure;
and
control a ramp rate of voltages applied to respective word lines in the selected block during respective verify phases of programming the memory cells in the selected block to balance programming speed against a peak current during the respective verify phases.

1 more element

A method for programming memory cells in a three-dimensional memory structure, wherein the memory cells are arranged as vertical NAND strings, the method comprising:

applying a program pulse to memory cells in a selected block in the three-dimensional memory structure during program phases of programming the memory cells in the selected block, wherein the selected block comprises word lines associated with the vertical NAND strings of the selected block;
and
controlling a ramp rate of voltages applied to respective word lines in the selected block during verify phases of programming the memory cells in the selected block in order to achieve a substantially identical peak current during the verify phases regardless of which word line in the selected block is selected for programming.

A non-volatile storage system comprising

a three-dimensional memory structure comprising a plurality of vertically oriented NAND strings having memory cells having control gates, the three-dimensional memory structure comprising a plurality of word lines, wherein each word line is connected to the control gates of memory cells on a group of the NAND strings, wherein ramping a voltage to the word lines associated with a group of the NAND strings at a default ramp rate during a verify phase when programming a selected word line has a default peak current;
and
one or more control circuits configured to:
program memory cells on a selected group of the NAND strings in the three-dimensional memory structure;
and
ramp voltages applied to respective word lines associated with the selected group of the NAND strings during verify phases of programming the memory cells connected to a first selected word line at a first rate that is faster than the default ramp rate in response to the first selected word line having a first default peak current for the default ramp rate that is below a target peak current while keeping a peak current during the verify phases within the target peak current.

3 more elements

Dependencies are inferred from the claim text.

Balancing peak power with programming speed in non-volatile memory

Life of this patent

Balancing peak power with programming speed in non-volatile memory

Life of this patent

Abstract

Claims20