Memory device and operation thereof
AssigneeYangtze Memory Technologies Co., Ltd.
InventorXiaojiang Guo
Life of this patent
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Abstract
A memory device includes an array of memory cells in a plurality of memory strings and arranged in a plurality of rows of memory cells. The memory device also includes a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform a read operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line, wherein the peripheral circuit is configured to apply a word line voltage on each of the plurality of word lines and determine a highest threshold voltage of the plurality of rows of memory cells based on a change of a word line capacitance loading in response to the word line voltage.
Claims20
A memory device, comprising:
- an array of memory cells in a plurality of memory strings and arranged in a plurality of rows of memory cells;
- a plurality of word lines respectively coupled to the plurality of rows of memory cells;
- and
- a peripheral circuit coupled to the plurality of word lines and configured to perform a read operation on a selected row of memory cells of the plurality of rows of memory cells, the selected row of memory cells being coupled to a selected word line, wherein the peripheral circuit is configured to:
- apply a word line voltage on each of the plurality of word lines;
- and
- determine a highest threshold voltage of the plurality of rows of memory cells based on a change of a word line capacitance loading in response to the word line voltage.
A system, comprising:
- a memory device configured to store data, the memory device comprising:
- an array of memory cells in a plurality of memory strings and arranged in a plurality of rows of memory cells;
- a plurality of word lines respectively coupled to the plurality of rows of memory cells;
- and
- a peripheral circuit coupled to the plurality of word lines and configured to perform a read operation on a selected row of memory cells of the plurality of rows of memory cells, the selected row of memory cells being coupled to a selected word line, wherein the peripheral circuit is configured to:
- apply a word line voltage on each of the plurality of word lines;
- and
- determine a highest threshold voltage of the plurality of rows of memory cells based on a change of a word line capacitance loading in response to the word line voltage, and
- a memory controller coupled to the memory device and configured to control the memory device.
A method for operating a memory device, the memory device comprising an array of memory cells in a plurality of memory strings and arranged in a plurality of rows of memory cells;
- and a plurality of word lines respectively coupled to the plurality of rows of memory cells, the method comprising performing a read operation on a selected row of memory cells of the plurality of rows of memory cells, the selected row of memory cells being coupled to a selected word line, wherein the performing the read operation comprises:
- applying a word line voltage on each of the plurality of word lines;
- and
- determining a highest threshold voltage of the plurality of rows of memory cells based on a change of a word line capacitance loading in response to the word line voltage.
Dependencies are inferred from the claim text.