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US 11,961,552 B2Granted
Memory device including partial pages in memory blocks
AssigneeSK hynix Inc.
InventorsSung Lae Oh, Jin Ho Kim, Sang Hyun Sung, Hyun Soo Shin
Life of this patent
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Abstract
A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction; and a cell region including a plane which is coupled to the plurality of bit lines, wherein the plane is divided into a plurality of memory groups each including a plurality of partial pages to be disposed in a plurality of rows in the first direction.
Claims19
A memory device comprising:
- a first wafer including a logic structure disposed on a top surface of the first wafer and a cell structure disposed on the bottom surface of the first wafer, wherein a cell region is disposed in the cell structure and a pass transistor circuit is disposed in the logic structure,
- a second wafer including a page buffer circuit, a peripheral circuit and a block switch circuit, and
- a plurality of bit lines extending in a first direction and arranged in a second direction,
- wherein the cell region includes a plane and is coupled to the plurality of bit lines,
- wherein the plane is divided into a plurality of memory groups, each including a plurality of partial pages, that are disposed in a plurality of rows arranged in the first direction.
2 more elements
A memory device comprising:
- a first wafer including a logic structure disposed on one surface of the first wafer and a cell structure disposed on the other surface of the first wafer, wherein the cell structure includes a cell region and the logic structure includes a pass transistor circuit,
- a second wafer including a page buffer circuit, a peripheral circuit and a block switch circuit, and
- a plurality of bit lines extending in a first direction and arranged in a second direction,
- wherein the cell region includes a plurality of memory blocks that are coupled to the plurality of bit lines,
- wherein each memory block is divided into a plurality of sub-blocks each including a plurality of partial pages that are disposed in a plurality of rows arranged in the first direction.
2 more elements
A memory device comprising:
- a first wafer including a logic structure and a cell structure disposed under the logic structure,
- a cell region disposed in the cell structure, and including a plurality of memory blocks, which are coupled to a plurality of bit lines that extend in a first direction and that are arranged in a second direction;
- a pass transistor circuit, disposed in the logic structure, that is configured to transfer an operating voltage to the plurality of memory blocks in response to a block selection signal;
- and
- a block switch circuit included in a second wafer, which overlaps with the first wafer in a vertical direction, that is configured to provide the block selection signal to the pass transistor circuit,
- wherein each memory block is divided into a plurality of sub-blocks each including a plurality of partial pages that are disposed in a plurality of rows arranged in the first direction.
3 more elements
Dependencies are inferred from the claim text.