Continuous dual path resistance detection for resistive temperature detectors in disk drives

A method for operating a data storage device comprising:

• biasing a first resistance of a resistive temperature detector (RTD) of a slider with a voltage bias, wherein the first resistance is electrically coupled to a first amplifier circuit on a low frequency (LF) path and a second amplifier circuit on a high frequency (HF) path;
• adding a bias pulse on the HF path to generate a HF resistance detection signal, wherein the second amplifier circuit is biased using the voltage bias and the bias pulse;
• chopping, on the LF path, a LF signal at the first amplifier circuit at a first clock frequency;
• and
• demodulating the chopped LF signal on the LF path using the first clock frequency to generate a LF resistance detection signal.

One or more processing devices of a data storage device comprising:

• means for biasing a first resistance of a resistive temperature detector (RTD) of a slider with a voltage bias, wherein the first resistance is electrically coupled to a first amplifier circuit on a low frequency (LF) path and a second amplifier circuit on a high frequency (HF) path;
• means for adding a bias pulse on the HF path to generate a HF resistance detection signal, wherein the second amplifier circuit is biased using the voltage bias and the bias pulse;
• means for chopping a LF signal at the first amplifier circuit at a first clock frequency;
• and
• means for demodulating the chopped LF signal on the LF path using the first clock frequency to generate a LF resistance detection signal.

Control circuitry comprising:

• a first amplifier circuit;
• a second amplifier circuit;
• a source for biasing a first resistance of a resistive temperature detector (RTD) with a voltage bias, wherein the first resistance is electrically coupled to the first amplifier circuit on a low frequency (LF) path and the second amplifier circuit on a high frequency (HF) path;
• a pulse generator for adding a bias pulse on the HF path to generate a HF resistance detection signal, wherein the second amplifier circuit is biased using the voltage bias and the bias pulse;
• a clock coupled to the first amplifier circuit on the LF path, wherein the clock chops a LF signal at the first amplifier circuit at a first clock frequency;
• and
• a demodulator demodulating, the chopped LF signal on the LF path using the first clock frequency to generate a LF resistance detection signal.