Liquid crystal display panel comprising pixel circuit reducing power consumption

A display panel, comprising:

• a plurality of first gate lines, a plurality of second gate lines, a plurality of data lines and a plurality of pixel cells arranged in an array;
• wherein each of the plurality of pixel cells comprises a plurality of sub-pixels, and each of the plurality of sub-pixels comprises a pixel circuit and a pixel electrode, one row of the plurality of sub-pixels correspond to one of the plurality of first gate lines and one of the plurality of second gate lines, and one column of the plurality of sub-pixels correspond to one of the plurality of data lines;
• wherein the pixel circuit comprises a first control circuit, a latch circuit, a second control circuit, a first input circuit and a second input circuit;
• wherein
• the first control circuit is configured to provide a signal on a data line to a first node under a control of a signal on a first gate line;
• the latch circuit is configured to latch signals of the first node and a second node;
• the second control circuit is configured to provide the signal on the data line to a third node under a control of a signal on a second gate line;
• the first input circuit is configured to provide a signal of a reference signal terminal to a pixel electrode under a control of the signal of the first node;
• and
• the second input circuit is configured to provide a signal of the third node to the pixel electrode under a control of the signal of the second node, the third node connecting the second control circuit and the second input circuit;
• wherein a first terminal of the first control circuit is directly connected to the data line, a second terminal of the first control circuit is connected to the first gate line, and a third terminal of the first control circuit is connected to the first node;
• a first terminal of the second control circuit is directly connected to a first terminal of the second input circuit, a second terminal of the second control circuit is connected to the second gate line, and a third terminal of the second control circuit is connected to the data line:
• a first terminal of the first input circuit is connected to a third terminal of the second input circuit, a second terminal of the first input circuit is connected to the first node, and a third terminal of the first input circuit is connected to the reference signal terminal;
• a second terminal of the second input circuit is connected to the second node;
• and
• the first terminal of the first input circuit and the third terminal of the second input circuit are both connected to the pixel electrode.