Display panel and display device

A display panel, comprising:

• at least one pixel circuit;
• and
• a light emitting element,
• wherein one pixel circuit of the at least one pixel circuit comprises a driving transistor, a second transistor, and a third transistor, wherein the second transistor is configured to provide a data signal to a source of the driving transistor, and the third transistor is configured to provide an adjusting voltage to the source of the driving transistor;
• wherein an operation process of the display panel comprises a data writing phase and a reset and adjustment phase;
• wherein during the data writing phase, the second transistor is turned on, the data signal is VData, a data line is configured to provide the data signal to the source of the driving transistor, a gate of the driving transistor is configured to receive the data signal, and a voltage of the gate of the driving transistor is VData+Vth, where Vth denotes a threshold voltage of the driving transistor;
• wherein, during the reset and adjustment phase, the third transistor is turned on, a voltage adjusting signal line is configured to provide the adjusting voltage to the source of the driving transistor, the adjusting voltage is VJ, a voltage of the source of the driving transistor is VJ, and the voltage of the gate of the driving transistor remains VData+Vth;
• and
• wherein VData+Vth−VJ≤−2V.

A display device, comprising a display panel, wherein the display panel comprises at least one pixel circuit and a light emitting element;

• wherein one pixel circuit of the at least one pixel circuit comprises a driving transistor, a second transistor, and a third transistor, wherein the second transistor is connected between a data line and a source of the driving transistor, and the third transistor is connected between a voltage adjusting signal line and the source of the driving transistor;
• wherein an operation process of the display panel comprises a data writing phase and a reset and adjustment phase;
• wherein, during the data writing phase, the second transistor is turned on, the data line is configured to provide a data signal to the source of the driving transistor, the data signal is VData, a gate of the driving transistor is configured to receive the data signal, and a voltage of the gate of the driving transistor is VData+Vth, where Vth denotes a threshold voltage of the driving transistor;
• wherein, during the reset and adjustment phase, the third transistor is turned on, the voltage adjusting signal line is configured to provide an adjusting voltage to the source of the driving transistor, a voltage of the source of the driving transistor is VJ, and the voltage of the gate of the driving transistor remains VData+Vth;
• and
• wherein VData+Vth−VJ≤−2V.