Display device

A display device comprising a pixel,

• wherein the pixel includes:
• a first transistor including a gate electrode electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node;
• a first capacitor formed between the first node and a fourth node;
• a second capacitor formed between the fourth node and a first power line;
• a second transistor including a gate electrode electrically connected to a first gate line, a first electrode electrically connected to a data line, and a second electrode electrically connected to the fourth node;
• a third transistor including a gate electrode electrically connected to a third gate line, a first electrode electrically connected to the first node, and a second electrode electrically connected to the third node;
• a fourth transistor including a gate electrode electrically connected to a second gate line, a first electrode electrically connected to the first node, and a second electrode electrically connected to a first initialization power line;
• an emission transistor including a gate electrode electrically connected to a fifth gate line, a first electrode electrically connected to the third node, and a second electrode electrically connected to a fifth node;
• a seventh transistor including a gate electrode electrically connected to a bypass control line, a first electrode electrically connected to the fifth node, and a second electrode electrically connected to a second initialization power line;
• and
• a light emitting element electrically connected between the fifth node and a second power line, and
• wherein the second initialization power line is different from the first initialization power line.

A display device comprising a pixel,

• wherein the pixel includes:
• a first transistor including a gate electrode electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node;
• a first capacitor formed between the first node and a first power line;
• a second transistor including a gate electrode electrically connected to a first gate line, a first electrode electrically connected to a data line, and a second electrode electrically connected to the second node;
• a third transistor including a gate electrode electrically connected to a third gate line, a first electrode electrically connected to the first node, and a second electrode electrically connected to the third node;
• a fourth transistor including a gate electrode electrically connected to a second gate line, a first electrode electrically connected to the first node, and a second electrode electrically connected to a first initialization power line;
• a fifth transistor including a gate electrode electrically connected to a fourth gate line, a first electrode electrically connected to the first power line, and a second electrode electrically connected to the second node;
• a sixth transistor including a gate electrode electrically connected to a fifth gate line, a first electrode electrically connected to the third node, and a second electrode electrically connected to a fifth node;
• and
• a light emitting element electrically connected between the fifth node and a second power line, and
• wherein the fifth gate line is different from the fourth gate line.