Shift register unit, driving method thereof, gate driving circuit, and display device

A shift register unit, comprising:

• an input circuit, respectively coupled to an input control terminal, a signal input terminal and a first node;
• a first capacitor circuit, a first terminal of the first capacitor circuit being coupled to a signal output terminal;
• an output circuit, respectively coupled to a second terminal of the first capacitor circuit, a first level signal input terminal and the signal output terminal;
• an output pull-down circuit, respectively coupled to a second node, the signal output terminal, and a second level signal input terminal;
• a coupling circuit, respectively coupled to the first level signal input terminal, the first node, and the second terminal of the first capacitor, configured to control to connect or disconnect the first node and the second terminal of the first capacitor circuit under the control of the first level signal input terminal;
• an inverter circuit, respectively coupled to the input control terminal, the first node, the second node, the first level signal input terminal, and the second level signal input terminal, and configured to control to connect or disconnect the second node and the first level signal input terminal under the control of the input control terminal, the first level signal input terminal and the first node, and configured to control to connect or disconnect the second node and the second level signal input terminal under the control of the first node and the second level signal input terminal;
• and
• a second reset circuit, respectively directly connected to a reset control terminal, the first level signal input terminal and the first node, and configured to control to connect or disconnect the first level signal input terminal and the first node under the control of the reset control terminal, wherein;
• the first level signal input terminal is configured to input a high level, the second level signal input terminal is configured to input a low level,
• wherein the input circuit includes a first transistor, a gate electrode of the first transistor is coupled to the input control terminal, and a first electrode of the first transistor is coupled to the signal input terminal, and a second electrode of the first transistor is coupled to the first node, wherein the inverter circuit
• comprises:
• a second transistor, a gate electrode of the second transistor being coupled to the first level signal input terminal, and a first electrode of the second transistor being coupled to the input control terminal, the first level signal input terminal and the input control terminal are different terminals;
• a third transistor, a gate electrode of the third transistor being coupled to the first node, a first electrode of the third transistor being coupled to a second electrode of the second transistor, a second electrode of the third transistor being coupled to the second level signal input terminal;
• a fourth transistor, a gate electrode of the fourth transistor being coupled to the second electrode of the second transistor, and a first electrode of the fourth transistor being coupled to the first level signal input terminal, a second electrode of the fourth transistor being coupled to the second node;
• and
• a fifth transistor, a gate electrode of the fifth transistor being coupled to the first node, a first electrode of the fifth transistor being coupled to the second node, and a second electrode of the fifth transistor being coupled to the second level signal input terminal,
• wherein the gate electrode of the first transistor and the first electrode of the second transistor are directly connected and connected to a same clock signal.