Pixel circuit

A pixel circuit comprising:

• a first transistor comprising a gate electrode coupled to a first node, a drain electrode coupled to a first power line, and a source electrode coupled to a second power line;
• a light emitting element coupled between the second power line and the first transistor;
• a second transistor coupled between a data line and the first node, the second transistor comprising a gate electrode coupled to a first scan line;
• a first capacitor coupled between the first node and the source electrode of the first transistor;
• a third transistor coupled between the first node and the second power line, the third transistor comprising a gate electrode coupled to a second node;
• a fourth transistor coupled between the second node and the data line, the fourth transistor comprising a gate electrode coupled to a second scan line;
• a second capacitor coupled between the second node and a first control line;
• a fifth transistor coupled between the second node and the first power line, the fifth transistor comprising a gate electrode coupled to a second control line;
• a sixth transistor coupled between the second capacitor and the first control line, the sixth transistor comprising a gate electrode coupled to a third control line;
• a third power line;
• and
• a seventh transistor coupled between a third node and the third power line, the seventh transistor comprising a gate electrode coupled to the second scan line,
• wherein the first transistor is an N-type transistor,
• wherein the second transistor is a P-type transistor, and
• wherein the first control line is configured to supply a voltage that is gradually reduced or gradually increased during a first period.

A pixel circuit comprising:

• a first transistor comprising a gate electrode coupled to a first node, a drain electrode coupled to a first power line, and a source electrode coupled to a second power line;
• a light emitting element coupled between the first power line and the first transistor;
• a second transistor coupled between a data line and the first node, the second transistor comprising a gate electrode coupled to a first scan line;
• a first capacitor coupled between the first node and the source electrode of the first transistor;
• a third transistor coupled between the first node and the second power line, the third transistor comprising a gate electrode coupled to a second node;
• a fourth transistor coupled between the second node and the data line, the fourth transistor comprising a gate electrode coupled to a second scan line;
• and
• a second capacitor coupled between the second node and a first control line, and comprising a first electrode to receive a voltage of the first control line and a second electrode to receive a data voltage of the data line.