Detection device and display device
AssigneeJapan Display Inc.
InventorTadayoshi Katsuta
Life of this patent
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Abstract
A detection device includes a plurality of detection elements arranged in a matrix having a row-column configuration in a detection area, a plurality of scan lines each coupled to the detection elements arranged in a first direction, a drive circuit configured to drive the scan lines, a plurality of output signal lines each coupled to the detection elements arranged in a second direction different from the first direction, and a detection circuit configured to be supplied with detection signals from the detection elements through the output signal lines.
Claims14
A detection device comprising:
- a plurality of detection elements arranged in a matrix having a row-column configuration in a detection area;
- a plurality of scan lines each coupled to the detection elements arranged in a first direction;
- a drive circuit configured to drive the scan lines;
- a plurality of output signal lines each coupled to the detection elements arranged in a second direction different from the first direction;
- and
- a detection circuit configured to be supplied with detection signals from the detection elements through the output signal lines, wherein
- the scan lines comprise reset control scan lines each configured to supply a reset control signal to apply a reset potential to the detection elements arranged in the first direction, and
- the drive circuit comprises:
- a first transistor configured to apply a first potential to each of the reset control scan lines;
- a second transistor that is coupled in series to the first transistor, and is configured to apply a second potential lower than the first potential to the reset control scan line;
- and
- a third transistor that is coupled in parallel to the second transistor, and is configured to apply the second potential to the reset control scan line.
A display device comprising:
- a plurality of display elements arranged in a matrix having a row-column configuration in a display area;
- a plurality of scan lines each coupled to the display elements arranged in a first direction;
- and
- a drive circuit configured to drive the scan lines, wherein
- the drive circuit comprises:
- a first transistor configured to apply a first potential to each of the scan lines, the first transistor being configured as a p-type thin-film transistor (TFT);
- a second transistor that is coupled in series to the first transistor, and is configured to apply a second potential lower than the first potential to the scan line;
- and
- a third transistor that is coupled in parallel to the second transistor, and is configured to apply the second potential to the scan line, the second and the third transistors being configured as n-type TFTs;
- a shift register;
- a negative AND (NAND) circuit configured to calculate a negative AND between an output of the shift register and an enable signal;
- and
- a logical inversion circuit configured to logically invert the output of the shift register,
- gates of the first and the second transistors are configured to receive an output of the NAND circuit, and
- a gate of the third transistor is configured to receive an output of the logical inversion circuit.
Dependencies are inferred from the claim text.