Handling integrated circuits in automated testing

Abstract

Apparatuses and methods are disclosed for handling integrated circuits in automated testing. The handler apparatus includes an upper assembly that is selectively translatable above a testing surface and a lower bracket extending from and positioned below the upper assembly. The lower bracket forms a first opening, is selectively moveable upward and downward, and includes a rotatable finger extending downward to pick up and place an integrated circuit in a socket. The handier may further include an image sensor to detect potential error conditions, and a tool extending from the lower bracket to open and close a lid on the socket. The methods include sensing an image of an integrated circuit during certain phases of testing, analyzing the image to determine if the integrated circuit is positioned correctly, and correcting any detected error conditions before continuing with the automated testing.

Dependencies are inferred from the claim text.