Fragment compression for coarse pixel shading

A data processing system comprising:

• a display device;
• a memory device to store pixel data for display via the display device;
• and
• a graphics processor to generate the pixel data, the graphics processor including:
• a graphics processor cache memory;
• and
• a processing cluster to perform multi-rate shading via coarse pixel shading, wherein the processing cluster includes circuitry to vary a shading rate via a coarse pixel shading operation on a coarse pixel quad fragment to generate a coarse pixel quad and output the coarse pixel quad;
• and
• a post-shader pixel pipeline including circuitry to:
• receive the coarse pixel quad from the processing cluster;
• perform coarse pixel operations on multiple coarse pixels within the coarse pixel quad via a pixel processing unit of the post-shader pixel pipeline;
• and
• write, via the post-shader pixel pipeline, a processed coarse pixel quad to a render cache.

A method of post shader pixel processing on a post-shader pixel pipeline, the method comprising:

• receiving a coarse pixel quad from a processing cluster configured to perform a multi-rate shading via coarse pixel shading operations on coarse pixel quad fragments to generate coarse pixel quads;
• varying a shading rate by performing coarse pixel operations on multiple coarse pixels within the coarse pixel quad via a pixel processing unit of the post-shader pixel pipeline;
• writing via the post-shader pixel pipeline, a processed coarse pixel quad to a render cache;
• evicting the processed coarse pixel quad from the render cache to a graphics processor cache memory as a coarse pixel;
• and
• writing the processed coarse pixel quad evicted to the graphics processor cache memory to a memory device as pixel data.