Information processing device

An information processing device comprising:

• a memory including a plurality of banks;
• a plurality of hash computation circuits;
• and
• an interconnect that respectively connects the banks in the memory and the hash computation circuits to each other, wherein
• the hash computation circuits of even number are assigned to a first half of a number of the banks of the memory,
• the hash computation circuits of odd number are assigned to a second half of a number of the banks of the memory,
• in each of the hash computation circuits, a selector, in which counter values are input from a counter that counts up by 1 per cycle with all initial counter values set to different values, selects read requests that respectively specify a bank with a bank number equal to the counter values such that the read requests from each of the hash computation circuits for reading data from the memory respectively specify different banks in a same cycle,
• a routing portion of the interconnect is set up so that arbitration of the read requests from each of the hash computation circuits does not occur by wire connection of butterfly connection,
• the memory memorizes DAG data calculated beforehand therein, DAG indicating directed acyclic graph files of a large dataset,
• the hash computation circuits each include a hash computation unit, a thread portion, a thread controller, an address-generation and bank-determination unit, FIFOs number of which is equal to number of the banks, a selector, and a counter,
• the hash computation unit performs hash computation based on DAG data read from the memory,
• the address-generation and bank-determination unit performs hash computation for input data based on a context of the thread portion to obtain a bank number of a bank and an address where DAG data to be accessed is stored, and stores each of the read requests in one of the FIFOs which has an equal number to the bank number,
• the counter has a different initial value and outputs the count value obtained by performing a counting operation in synchronization to the selector, and
• the selector determines the FIFO based on a counter value to be input thereto.