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US 11,960,987 B2Granted
Discrete three-dimensional processor
AssigneesHangZhou HaiCun Information Technology Co., Ltd., Guobiao Zhang
InventorGuobiao Zhang
Life of this patent
Estimating the term…
Abstract
A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.
Claims18
A discrete three-dimensional (3-D) processor, comprising:
- a plurality of storage-processing units (SPU's), each of said SPU's comprising a non-memory circuit and more than one 3-D memory (3D-M) array;
- a first die on a first semiconductor substrate, wherein said 3D-M array comprises memory cells stacked above said first semiconductor substrate, and an in-die peripheral-circuit component of said 3D-M array is disposed on said first semiconductor substrate;
- a second die on a second semiconductor substrate, wherein at least a portion of said non-memory circuit and an off-die peripheral-circuit component of said 3D-M array are disposed on said second semiconductor substrate;
- wherein, said non-memory circuit is not a part of a memory;
- said first die does not comprise said off-die peripheral-circuit component;
- said first and second dice are communicatively coupled by a plurality of inter-die connections;
- said first and second semiconductor substrates are separate semiconductor substrates.
4 more elements
Dependencies are inferred from the claim text.