Artificial neural network computation using integrated circuit devices having analog inference capability

A device, comprising:

• a buffer;
• an inference logic circuit;
• voltage drivers;
• and
• memory cells;
• wherein the device is configured to receive, in the buffer, image data having pixel values;
• and
• wherein the inference logic circuit is configured to:
• generate, from the pixel values, inputs to a set of artificial neurons;
• identify a region of the memory cells having threshold voltages programmed to represent a weight matrix for the set of artificial neurons;
• instruct the voltage drivers to apply first voltages to the region of the memory cells according to the inputs;
• obtain, based on the region of the memory cells responsive to the first voltages, first data from an operation of multiplication and accumulation applied on the weight matrix and the inputs;
• and
• apply activation functions of the set of artificial neurons to the first data to generate second data representative of outputs of the set of artificial neurons.

An apparatus, comprising:

• a first integrated circuit die having an image sensing pixel array;
• a second integrated circuit die having an image processing logic circuit, and an inference logic circuit;
• a third integrated circuit die having a plurality of layers, each containing an array of memory cells having threshold voltages programmable to store data;
• an integrated circuit package configured to enclose the first integrated circuit die, the second integrated circuit die and the third integrated circuit die;
• a buffer;
• an interface;
• and
• voltage drivers;
• wherein the image processing logic circuit is configured to write image data having pixel values, representative of an image captured by the image sensing pixel array, into the buffer in response to a command received in the interface;
• and
• wherein the inference logic circuit is configured to:
• generate, from the pixel values, inputs to a set of artificial neurons;
• identify a region of memory cells in the third integrated circuit die having threshold voltages programmed to represent a weight matrix for the set of artificial neurons;
• instruct the voltage drivers to apply read voltages to the region of memory cells according to the inputs;
• obtain, based on the region of memory cells responsive to the read voltages, first data from an operation of multiplication and accumulation applied on the weight matrix and the inputs;
• and
• apply activation functions of the set of artificial neurons to the first data to generate a second data representative of outputs of the set of artificial neurons.