Inter-thread interrupt signal sending based on interrupt configuration information of a PCI device and thread status information

A computing device having one or more processing units and one or more storage devices, the one or more storage devices individually or collectively storing computer executable instructions, which when executed by the one or more processing units, enable the one or more processing units to individually or collectively implement acts comprising:

• receiving, via a peripheral component interconnect (PCI) bus, a notification message from a first processor in which a first thread is located, the notification message related to a virtual space address of the first thread to which a memory address of a memory mapped I/O (MMIO) memory of a PCI device is mapped;
• generating an interrupt signal for a second thread in response to receiving the notification message;
• configuring interrupt configuration information of the PCI device based on status information of the second thread that includes whether the second thread is running or a running status of the second thread, the configuring the interrupt configuration information including configuring an interrupt signal sending mechanism as sending the interrupt signal to a physical processor in a host kernel corresponding to a second processor in which the second thread is located in response to the second thread being assigned in a guest kernel and the second thread being not running and the second processor being a virtual processor, the physical processor being configured to wake up the virtual processor;
• and
• sending the interrupt signal to the second processor in which the second thread is located based on the interrupt configuration information of the PCI device.

A non-transitory computer storage medium having computer executable instructions stored thereon, which when executed by one or more processing units, enable the one or more processing units to individually or collectively implement acts comprising:

• receiving, via a peripheral component interconnect (PCI) bus, a notification message from a first processor in which a first thread is located, the notification message related to a virtual space address of the first thread to which a memory address of a memory mapped I/O (MMIO) memory of a PCI device is mapped;
• generating an interrupt signal for a second thread in response to receiving the notification message;
• configuring interrupt configuration information of the PCI device based on status information of the second thread that includes whether the second thread is running or a running status of the second thread, the configuring the interrupt configuration information including configuring an interrupt signal sending mechanism as sending the interrupt signal to a physical processor in a host kernel corresponding to a second processor in which the second thread is located in response to the second thread being assigned in a guest kernel and the second thread being not running and the second processor being a virtual processor, the physical processor being configured to wake up the virtual processor;
• and
• sending the interrupt signal to the second processor in which the second thread is located based on the interrupt configuration information of the PCI device.