Technologies for fast booting with error-correcting code memory
AssigneeIntel Corporation
InventorsMurugasamy K. Nachimuthu, Rajat Agarwal, Mohan J. Kumar
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Abstract
Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.
Claims24
A compute device comprising:
- a plurality of processors;
- an error-correcting code (ECC) memory;
- and
- circuitry included in at least a portion of the plurality of processors to execute a basic input/output system (BIOS), the BIOS to:
- cause a hardware accelerator to initialize a plurality of memory addresses of the ECC memory via a plurality of direct-store operations that include the hardware accelerator to access the plurality of memory addresses without going through a cache hierarchy of any of the plurality of processors.
A method for booting a compute device, the method comprising:
- executing, by circuitry included in at least a portion of a plurality of processors, a basic input/output system (BIOS), the BIOS to cause initializing, by a hardware accelerator, a plurality of memory addresses of an error-correcting code (ECC) memory via a plurality of direct-store operations that include the hardware accelerator accessing the plurality of memory addresses without going through a cache hierarchy of any of the plurality of processors.
One or more non-transitory computer-readable media comprising a plurality of instructions stored thereon that, when executed, causes a compute device to:
- execute, by circuitry included in at least a portion of a plurality of processors, a basic input/output system (BIOS), the BIOS to cause a hardware accelerator to initialize, a plurality of memory addresses of an error-correcting code (ECC) memory via a plurality of direct-store operations that include the hardware accelerator to access the plurality of memory addresses without going through a cache hierarchy of any of the plurality of processors.
Dependencies are inferred from the claim text.